xiaowei li (23 Ergebnisse)

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Paperback. Zustand: Brand New. 316 pages. 9.25x6.10x0.67 inches. In Stock.

Taschenbuch. Zustand: Neu. Frontiers of Algorithmics | 17th International Joint Conference, IJTCS-FAW 2023 Macau, China, August 14-18, 2023 Proceedings | Minming Li (u. a.) | Taschenbuch | Lecture Notes in Computer Science | xx | Englisch | 2023 | Springer | EAN 9783031393433 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.

Zustand: Hervorragend. Zustand: Hervorragend | Seiten: 316 | Sprache: Englisch | Produktart: Bücher | This book constitutes the refereed proceedings of the 17th International Joint Conference on Theoretical Computer Science-Frontier of Algorithmic Wisdom (IJTCS-FAW 2023), consisting of the 17th International Conference on Frontier of Algorithmic Wisdom (FAW) and the 4th International Joint Conference on Theoretical Computer Science (IJTCS), held in Macau, China, during August 14¿18, 2023. FAW started as the Frontiers of Algorithmic Workshop in 2007 at Lanzhou, China, and was held annually from 2007 to 2021 and published archival proceedings. IJTCS, the International joint theoretical Computer Science Conference, started in 2020, aimed to bring in presentations covering active topics in selected tracks in theoretical computer science. To accommodate the diversified new research directions in theoretical computer science, FAW and IJTCS joined their forces together to organize an event for information exchange of new findings and work of enduring value in the field. The 21 full papers included in this book were carefully reviewed and selected from 34 submissions. They were organized in topical sections as follows: algorithmic game theory; algorithms and data structures; combinatorial optimization; and computational economics.

Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book constitutes the refereed proceedings of the 17th International Joint Conference on Theoretical Computer Science-Frontier of Algorithmic Wisdom (IJTCS-FAW 2023), consisting of the 17th International Conference on Frontier of Algorithmic Wisdom (FAW) and the 4th International Joint Conference on Theoretical Computer Science (IJTCS), held in Macau, China, duringAugust 14-18, 2023.FAW started as the Frontiers of Algorithmic Workshop in 2007 at Lanzhou, China, and was held annually from 2007 to 2021 and published archival proceedings. IJTCS, the International joint theoretical Computer Science Conference, started in 2020, aimed to bring in presentations covering active topics in selected tracks in theoretical computer science. To accommodate the diversified new research directions in theoretical computer science, FAW and IJTCS joined their forces together to organize an event for information exchange of new findings and work of enduring value in the field. The 21 full papers included in this book were carefully reviewed and selected from 34 submissions. They were organized in topical sections as follows: algorithmic game theory; algorithms and data structures; combinatorial optimization; and computational economics.

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Zustand: Hervorragend. Zustand: Hervorragend | Seiten: 324 | Sprache: Englisch | Produktart: Bücher | With the end of Dennard scaling and Moore¿s law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or ¿3S¿ for short. We then explore the use of 3S for general IC designs, general-purpose processors, network-on-chip (NoC) and deep learning accelerators, and present prototypes to demonstrate how 3S responds to in-field silicon degradation and recovery under various runtime faults caused by aging, process variations, or radical particles. Moreover, we demonstrate that 3S not onlyoffers a powerful backbone for various on-chip fault-tolerant designs and implementations, but also has farther-reaching implications such as maintaining graceful performance degradation, mitigating the impact of verification blind spots, and improving chip yield. This book is the outcome of extensive fault-tolerant computing research pursued at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences over the past decade. The proposed built-in on-chip fault-tolerant computing paradigm has been verified in a broad range of scenarios, from small processors in satellite computers to large processors in HPCs. Hopefully, it will provide an alternative yet effective solution to the growing reliability challenges for large-scale VLSI designs.

Hardcover. Zustand: Brand New. 264 pages. 9.25x6.10x0.83 inches. In Stock.

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Softcover. Zustand: gut. 2023. Frontiers of Algorithmics In deutscher Sprache. pages.

Taschenbuch. Zustand: Neu. Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design | A Self-Test, Self-Diagnosis, and Self-Repair-Based Approach | Xiaowei Li (u. a.) | Taschenbuch | xviii | Englisch | 2024 | Springer | EAN 9789811985539 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.

Buch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - With the end of Dennard scaling and Moore's law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or '3S' for short. We then explore the use of 3S for general IC designs, general-purpose processors, network-on-chip (NoC) and deep learning accelerators, and present prototypes to demonstrate how 3S responds to in-field silicon degradation and recovery under various runtime faults caused by aging, process variations, or radical particles. Moreover, we demonstrate that 3S not onlyoffers a powerful backbone for various on-chip fault-tolerant designs and implementations, but also has farther-reaching implications such as maintaining graceful performance degradation, mitigating the impact of verification blind spots, and improving chip yield.This book is the outcome of extensive fault-tolerant computing research pursued at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences over the past decade. The proposed built-in on-chip fault-tolerant computing paradigm has been verified in a broad range of scenarios, from small processors in satellite computers to large processors in HPCs. Hopefully, it will provide an alternative yet effective solution to the growing reliability challenges for large-scale VLSI designs.

Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - With the end of Dennard scaling and Moore's law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or '3S' for short. We then explore the use of 3S for general IC designs, general-purpose processors, network-on-chip (NoC) and deep learning accelerators, and present prototypes to demonstrate how 3S responds to in-field silicon degradation and recovery under various runtime faults caused by aging, process variations, or radical particles. Moreover, we demonstrate that 3S not onlyoffers a powerful backbone for various on-chip fault-tolerant designs and implementations, but also has farther-reaching implications such as maintaining graceful performance degradation, mitigating the impact of verification blind spots, and improving chip yield.This book is the outcome of extensive fault-tolerant computing research pursued at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences over the past decade. The proposed built-in on-chip fault-tolerant computing paradigm has been verified in a broad range of scenarios, from small processors in satellite computers to large processors in HPCs. Hopefully, it will provide an alternative yet effective solution to the growing reliability challenges for large-scale VLSI designs.

Hardcover. Zustand: Brand New. 322 pages. 9.25x6.10x0.75 inches. In Stock.

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