kourtev ivan (15 Ergebnisse)

Zustand: Very Good. 1st Edition. Former library book; may include library markings. Used book that is in excellent condition. May show signs of wear or have minor defects.

hardcover. Zustand: Very Good. Zustand des Schutzumschlags: No Dust Jacket. Name from previous owner on FEP. Otherwise like new. No dust jacket. MB. Used.

hardcover. Zustand: Very Good. Zustand des Schutzumschlags: No Dust Jacket. First Edition. Orange hardcover and contents in almost new condition, showing minimal signs of wear. Previous owner's name on FEP. Profusely illustrated by diagrams and tables. No dust jacket. T. Used.

Zustand: New. pp. 284 52:B&W 6.14 x 9.21in or 234 x 156mm (Royal 8vo) Case Laminate on White w/Gloss Lam.

Zustand: New. This is a Brand-new US Edition. This Item may be shipped from US or any other country as we have multiple locations worldwide.

Gebunden. Zustand: New.

Zustand: New.

Zustand: Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher.

Taschenbuch. Zustand: Neu. Timing Optimization Through Clock Skew Scheduling | Ivan S. Kourtev (u. a.) | Taschenbuch | xxi | Englisch | 2012 | Springer | EAN 9781461369851 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.

Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - History of the Book The last three decades have witnessed an explosive development in - tegrated circuit fabrication technologies. The complexities of current CMOS circuits are reaching beyond the 65 nanometer feature size and multi-hundred million transistors per integrated circuit. To fully exploit this technological potential, circuit designers use sophisticated Computer-Aided Design (CAD) tools. While supporting the talents of innumerable microelectronics engineers, these CAD tools have become the enabling factor responsible for the succe- ful design and implementation of thousands of high performance, large scale integrated circuits. This book (a research monograph) originated from a body of doctoral d- sertationresearchcompletedbythe rstauthorattheUniversityofRochester from 1994 to 1999 while under the supervision of Prof. Eby G. Friedman. This research focuses on issues in the design of the clock distribution network in large scale, high performance digital synchronous circuits and particularly, on algorithmsfornon-zero clockskewscheduling.Duringthedevelopmentofthis research, it became clear that incorporating timing issues into the successful integrated circuit design process is of fundamental importance, particularly in that advanced theoretical developments in this area have been slow to reach the designers' desktops. The second edition of the book is enhanced by the body of doctoral dissertation research completed by the second author at the University of Pittsburgh from 2000 to 2005 under the supervision of Prof.

Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - History of the Book The last three decades have witnessed an explosive development in integrated circuit fabrication technologies. The complexities of cur rent CMOS circuits are reaching beyond the 100 nanometer feature size and multi-hundred million transistors per integrated circuit. To fully exploit this technological potential, circuit designers use sophisticated Computer-Aided Design (CAD) tools. While supporting the talents of innumerable microelectronics engineers, these CAD tools have become the enabling factor responsible for the successful design and implemen tation of thousands of high performance, large scale integrated circuits. This research monograph originated from a body of doctoral disserta tion research completed by the first author at the University of Rochester from 1994 to 1999 while under the supervision of Prof. Eby G. Friedman. This research focuses on issues in the design of the clock distribution net work in large scale, high performance digital synchronous circuits and particularly, on algorithms for non-zero clock skew scheduling. During the development of this research, it has become clear that incorporating timing issues into the successful integrated circuit design process is of fundamental importance, particularly in that advanced theoretical de velopments in this area have been slow to reach the designers' desktops.

Zustand: Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher.

Buch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - History of the Book The last three decades have witnessed an explosive development in - tegrated circuit fabrication technologies. The complexities of current CMOS circuits are reaching beyond the 65 nanometer feature size and multi-hundred million transistors per integrated circuit. To fully exploit this technological potential, circuit designers use sophisticated Computer-Aided Design (CAD) tools. While supporting the talents of innumerable microelectronics engineers, these CAD tools have become the enabling factor responsible for the succe- ful design and implementation of thousands of high performance, large scale integrated circuits. This book (a research monograph) originated from a body of doctoral d- sertationresearchcompletedbythe rstauthorattheUniversityofRochester from 1994 to 1999 while under the supervision of Prof. Eby G. Friedman. This research focuses on issues in the design of the clock distribution network in large scale, high performance digital synchronous circuits and particularly, on algorithmsfornon-zero clockskewscheduling.Duringthedevelopmentofthis research, it became clear that incorporating timing issues into the successful integrated circuit design process is of fundamental importance, particularly in that advanced theoretical developments in this area have been slow to reach the designers' desktops. The second edition of the book is enhanced by the body of doctoral dissertation research completed by the second author at the University of Pittsburgh from 2000 to 2005 under the supervision of Prof.

Buch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - History of the Book The last three decades have witnessed an explosive development in integrated circuit fabrication technologies. The complexities of cur rent CMOS circuits are reaching beyond the 100 nanometer feature size and multi-hundred million transistors per integrated circuit. To fully exploit this technological potential, circuit designers use sophisticated Computer-Aided Design (CAD) tools. While supporting the talents of innumerable microelectronics engineers, these CAD tools have become the enabling factor responsible for the successful design and implemen tation of thousands of high performance, large scale integrated circuits. This research monograph originated from a body of doctoral disserta tion research completed by the first author at the University of Rochester from 1994 to 1999 while under the supervision of Prof. Eby G. Friedman. This research focuses on issues in the design of the clock distribution net work in large scale, high performance digital synchronous circuits and particularly, on algorithms for non-zero clock skew scheduling. During the development of this research, it has become clear that incorporating timing issues into the successful integrated circuit design process is of fundamental importance, particularly in that advanced theoretical de velopments in this area have been slow to reach the designers' desktops.

Zustand: New. This work focuses on optimizing the timing of large-scale, high-performance, digital synchronous systems. A particular emphasis is placed on algorithms for non-zero clock skew scheduling to improve the performance and reliability of VLSI circuits. Num Pages: 194 pages, biography. BIC Classification: TJFC; UY. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 14. Weight in Grams: 488. . 2000. Hardback. . . . . Books ship from the US and Ireland.