Gizopoulos dimitris (24 Ergebnisse)

Zustand: New. Brand New. Soft Cover International Edition. Different ISBN and Cover Image. Priced lower than the standard editions which is usually intended to make them more affordable for students abroad. The core content of the book is generally the same as the standard edition. The country selling restrictions may be printed on the book but is no problem for the self-use. This Item maybe shipped from US or any other country as we have multiple locations worldwide.…

xxii, 281 p. Hardcover. Versand aus Deutschland / We dispatch from Germany via Air Mail. Einband bestoßen, daher Mängelexemplar gestempelt, sonst sehr guter Zustand. Imperfect copy due to slightly bumped cover, apart from this in very good condition. Stamped. Sprache: Englisch.

Zustand: Gebraucht / Used. Fine state d582e.

Paperback. Zustand: Brand New. 400 pages. 9.25x6.10x9.21 inches. In Stock.

Taschenbuch. Zustand: Neu. Advanced Parallel Processing Technologies | 16th International Symposium, APPT 2025, Athens, Greece, July 13-16, 2025, Proceedings | Chao Li (u. a.) | Taschenbuch | Lecture Notes in Computer Science | xvii | Englisch | 2025 | Springer | EAN 9789819510207 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.…

Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book constitutes the refereed proceedings of the 16th International Symposium on Advanced Parallel Processing Technologies, APPT 2025, held in Athens, Greece, during July 13 16, 2025.The 17 full papers and 10 short papers included in this book were carefully reviewed and selected from 74 submissions. They were organized in topical sections as follows: Chip and Accelerators, Memory and Storage, Cloud and Networking, Design for LLM and ML/AI, Big Data and Graph Processing, and Secure and Dependable System.…

Zustand: Sehr gut. Zustand: Sehr gut | Seiten: 440 | Sprache: Englisch | Produktart: Bücher | Advances in Electronic Testing: Challenges and Methodologies is a new type of edited volume in the Frontiers in Electronic Testing book series devoted to recent advances in electronic circuits testing. The book is a comprehensive elaboration on important topics which capture major research and development efforts today. The motivation and inspiration behind this book is to deliver a thorough text that focuses on the evolution of test technology, provides insight about the abiding importance of discussed topics, records today¿s state of the art and industrial practices and trends, reveals the challenges for emerging testing methodologies, and envisages the future of this journey. The book consists of eleven edited chapters written by experts in Defect-Oriented Testing, Nanometer Technologies Failures and Testing, Silicon Debug, Delay Testing, High-Speed Test Interfaces, DFT-Oriented Low-Cost Testers, Embedded Cores and System-on-Chip Testing, Memory Testing, Mixed-Signal Testing, RF Testing and Loaded Board Testing. Contributing authors are affiliated with (in alphabetical order) Agilent, ARM, Balearic Islands Univ., IBM, Inovys, Intel, LogicVision, Magma, Mentor Graphics, New Mexico Univ., Sandia National Labs, Synopsys, Teradyne and Texas Instruments. Advances in Electronic Testing: Challenges and Methodologies is an advanced textbook and reference point for senior undergraduate and graduate students in MSc or PhD tracks, professors and research leaders in the electronic testing domain. It is also for industry design and test engineers and managers seeking a global view and understanding of test technology practices and methodologies and a dense elaboration on test-related issues they face in their development projects. "There is a definite need for documenting the advances in testing ¿ I find the work of this edited volume by Dimitris Gizopoulos and his team of authors to be significant and timely. [¿] the book provides, besidesnovel test methodologies, a collective insight into the emerging aspects of testing. This, I think, is beneficial to practicing engineers and researchers both of whom must stay at the forefront of technology. [¿] This latest addition to the Frontiers Series is destined to serve an important role." From the Foreword by Vishwani D. Agrawal, Consulting Editor, Frontiers in Electronic Testing Book Series.…

Taschenbuch. Zustand: Neu. Dependable Multicore Architectures at Nanoscale | Marco Ottavi (u. a.) | Taschenbuch | xxii | Englisch | 2018 | Springer | EAN 9783319853918 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu. …

Zustand: New. In English.

Buch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book provides comprehensive coverage of the dependability challenges in today's advanced computing systems. It is an in-depth discussion of all the technological and design-level techniques that may be used to overcome these issues and analyzes various dependability-assessment methods. The impact of individual application scenarios on the definition of challenges and solutions is considered so that the designer can clearly assess the problems and adjust the solution based on the specifications in question. The book is composed of three sections, beginning with an introduction to current dependability challenges arising in complex computing systems implemented with nanoscale technologies, and of the effect of the application scenario. The second section details all the fault-tolerance techniques that are applicable in the manufacture of reliable advanced computing devices. Different levels, from technology-level fault avoidance to the use of error correcting codes and system-level checkpointing are introduced and explained as applicable to the different application scenario requirements. Finally the third section proposes a roadmap of future trends in and perspectives on the dependability and manufacturability of advanced computing systems from the special point of view of industrial stakeholders. Dependable Multicore Architectures at Nanoscale showcases the original ideas and concepts introduced into the field of nanoscale manufacturing and systems reliability over nearly four years of work within COST Action IC1103 MEDIAN, a think-tank with participants from 27 countries. Academic researchers and graduate students working in multi-core computer systems and their manufacture will find this book of interest as will industrial design and manufacturing engineers working in VLSI companies.…

Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book provides comprehensive coverage of the dependability challenges in today's advanced computing systems. It is an in-depth discussion of all the technological and design-level techniques that may be used to overcome these issues and analyzes various dependability-assessment methods. The impact of individual application scenarios on the definition of challenges and solutions is considered so that the designer can clearly assess the problems and adjust the solution based on the specifications in question. The book is composed of three sections, beginning with an introduction to current dependability challenges arising in complex computing systems implemented with nanoscale technologies, and of the effect of the application scenario. The second section details all the fault-tolerance techniques that are applicable in the manufacture of reliable advanced computing devices. Different levels, from technology-level fault avoidance to the use of error correcting codes and system-level checkpointing are introduced and explained as applicable to the different application scenario requirements. Finally the third section proposes a roadmap of future trends in and perspectives on the dependability and manufacturability of advanced computing systems from the special point of view of industrial stakeholders. Dependable Multicore Architectures at Nanoscale showcases the original ideas and concepts introduced into the field of nanoscale manufacturing and systems reliability over nearly four years of work within COST Action IC1103 MEDIAN, a think-tank with participants from 27 countries. Academic researchers and graduate students working in multi-core computer systems and their manufacture will find this book of interest as will industrial design and manufacturing engineers working in VLSI companies.…

Hardcover. Zustand: Brand New. 300 pages. 9.25x6.25x0.75 inches. In Stock.

Zustand: New. In English.

Zustand: New. In English.

Taschenbuch. Zustand: Neu. Embedded Processor-Based Self-Test | Dimitris Gizopoulos (u. a.) | Taschenbuch | xv | Englisch | 2011 | Springer US | EAN 9781441952523 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.…

Zustand: New. In English.

Gebunden. Zustand: New. Inhaltsverzeichnisrnrnn Part I: Design techniques to improve the resilience of computing systemsn Chapter 1: Technological layern Chapter 2: Design techniques to improve the resilience of computing systems: logic layer.

Paperback. Zustand: Brand New. 232 pages. 9.00x6.00x0.60 inches. In Stock.

Hardcover. Zustand: Brand New. 1st edition. 216 pages. 9.50x6.50x0.50 inches. In Stock.

Buch. Zustand: Neu. Neuware - Reliability has always been a major concern in designing computing systems. However, the increasing complexity of such systems has led to a situation where efforts for assuring reliability have become extremely costly, both for the design of solutions for the mitigation of possible faults, and for the reliability assessment of such techniques. Cross-layer reliability is fast becoming the preferred solution. In a cross-layer resilient system, physical and circuit level techniques can mitigate low-level faults. Hardware redundancy can be used to manage errors at the hardware architecture layer. Eventually, software implemented error detection and correction mechanisms can manage those errors that escaped the lower layers of the stack. This book presents state-of-the-art solutions for increasing the resilience of computing systems, both at single levels of abstraction and multi-layers. The book begins by addressing design techniques to improve the resilience of computing systems, covering the logic layer, the architectural layer and the software layer. The second part of the book focuses on cross-layer resilience, including coverage of physical stress, reliability assessment approaches, fault injection at the ISA level, analytical modelling for cross-later resiliency, and stochastic methods. Cross-Layer Reliability of Computing Systems is a valuable resource for researchers, postgraduate students and professional computer architects focusing on the dependability of computing systems.…

Hardcover. Zustand: Brand New. 412 pages. 9.75x6.50x0.75 inches. In Stock.

Zustand: New. In English.

Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - Embedded Processor-Based Self-Test is a guide to self-testing strategies for embedded processors. Embedded processors are regularly used today in most System-on-Chips (SoCs). Testing of microprocessors and embedded processors has always been a challenge because most traditional testing techniques fail when applied to them. This is due to the complex sequential structure of processor architectures, which consists of high performance datapath units and sophisticated control logic for performance optimization. Structured Design-for-Testability (DfT) and hardware-based self-testing techniques, which usually have a non-trivial impact on a circuit's performance, size and power, can not be applied without serious consideration and careful incorporation into the processor design.Embedded Processor-Based Self-Test shows how the powerful embedded functionality that processors offer can be utilized as a self-testing resource. Through a discussion of different strategies the book emphasizes on the emerging area of Software-Based Self-Testing (SBST). SBST is based on the idea of execution of embedded software programs to perform self-testing of the processor itself and its surrounding blocks in the SoC. SBST is a low-cost strategy in terms of overhead (area, speed, power), development effort and test application cost, as it is applied using low-cost, low-speed test equipment.Embedded Processor-Based Self-Test can be used by designers, DfT engineers, test practitioners, researchers and students working on digital testing, and in particular processor and SoC test. This book sets the framework for comparisons among different SBST methodologies by discussing key requirements. It presents successful applications of SBST to a number of embedded processors of different complexities and instruction set architectures.…

Buch. Zustand: Neu. Neuware - Embedded Processor-Based Self-Test is a guide to self-testing strategies for embedded processors. Embedded processors are regularly used today in most System-on-Chips (SoCs). Testing of microprocessors and embedded processors has always been a challenge because most traditional testing techniques fail when applied to them. This is due to the complex sequential structure of processor architectures, which consists of high performance datapath units and sophisticated control logic for performance optimization. Structured Design-for-Testability (DfT) and hardware-based self-testing techniques, which usually have a non-trivial impact on a circuit s performance, size and power, can not be applied without serious consideration and careful incorporation into the processor design.Embedded Processor-Based Self-Test shows how the powerful embedded functionality that processors offer can be utilized as a self-testing resource. Through a discussion of different strategies the book emphasizes on the emerging area of Software-Based Self-Testing (SBST). SBST is based on the idea of execution of embedded software programs to perform self-testing of the processor itself and its surrounding blocks in the SoC. SBST is a low-cost strategy in terms of overhead (area, speed, power), development effort and test application cost, as it is applied using low-cost, low-speed test equipment.Embedded Processor-Based Self-Test can be used by designers, DfT engineers, test practitioners, researchers and students working on digital testing, and in particular processor and SoC test. This book sets the framework for comparisons among different SBST methodologies by discussing key requirements. It presents successful applications of SBST to a number of embedded processors of different complexities and instruction set architectures.…