Logic Synthesis and SOC Prototyping: RTL Design using VHDL - Softcover

Taraate, Vaibbhav

 
9789811513169: Logic Synthesis and SOC Prototyping: RTL Design using VHDL
Softcover
ISBN 10: 9811513163 ISBN 13: 9789811513169
Verlag: Springer, 2021

Inhaltsangabe

This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book gives practical information on the issues in SOC and ASIC prototyping using modern high-density FPGAs. The book covers SOC performance improvement techniques, testing, and system-level verification. The book also describes the modern Xilinx FPGA architecture and their use in SOC prototyping. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design. The contents of this book will be of use to students, professionals, and hobbyists alike.


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Über die Autorin bzw. den Autor

Vaibbhav Taraate is Entrepreneur and Mentor at “1 Rupee S T”. He holds a B.E. (Electronics) degree from Shivaji University, Kolhapur, in 1995 and secured a gold medal for standing first in all engineering branches. He has completed his M.Tech. (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 15 years ofexperience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.

Von der hinteren Coverseite

This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book gives practical information on the issues in SOC and ASIC prototyping using modern high-density FPGAs. The book covers SOC performance improvement techniques, testing, and system-level verification. The book also describes the modern Xilinx FPGA architecture and their use in SOC prototyping. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design. The contents of this book will be of use to students, professionals, and hobbyists alike.


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Verlag
Springer
Erscheinungsdatum
2021
Sprache
Englisch
ISBN 10 
9811513163
ISBN 13 
9789811513169
Einband
Taschenbuch
Auflage
1
Anzahl der Seiten
270
Kontakt zum Hersteller
ProductSafety@springernature.com
ProductSafety@springernature.com

Poststr. 9
Darmstadt
64293
Deutschland

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9789811513138: Logic Synthesis and SOC Prototyping: RTL Design using VHDL

Vorgestellte Ausgabe

ISBN 10:  9811513139 ISBN 13:  9789811513138
Verlag: Springer, 2020
Hardcover