Power Distribution Networks with On-Chip Decoupling Capacitors - Softcover

Über die Autorin bzw. den Autor

Eby G. Friedman was born in Jersey City, New Jersey in 1957. He received the B. S. degree from Lafayette College, Easton, Pennsylvania in 1979, and the M. S. and Ph. D. degrees from the University of California, Irvine, in 1981 and 1989, respectively, all in electrical engineering. He was with Philips Gloeilampen Fabrieken, Eindhoven, The Netherlands, in 1978 where he worked on the design of bipolar differential amplifiers. From 1979 to 1983, he was employed by Hughes Aircraft Company, Newport Beach, California, working in the areas of custom IC design, software compatible gate array design, one- and two-dimensional device modeling, circuit modeling, and double level metal process development. From 1983 to 1991, he was employed at Hughes Aircraft Company, Carlsbad, California, rising to the position of Manager of the Signal Processing Design and Test Department, responsible for the design and test of high performance VLSI/VHSIC CMOS and BIMOS digital and analog IC's, the development of supporting design and test methodologies and CAD tools, functional and parametric test, and the development of high performance and high resolution DSP and oversampled systems. Dr. Friedman has been with the Department of Electrical and Computer Engineering at the University of Rochester, Rochester, New York, since 1991, where he is a Distinguished Professor and Director of the High Performance VLSI/IC Design and Analysis Laboratory. He previously was the Director of the Center for Electronic Imaging Systems. He is also a Visiting Professor at the Technion - Israel Institute of Technology. He also directs the Technion Advanced Circuits Research Center (ACRC). His current research and teaching interests are in high performance synchronous digital and mixed-signal microelectronic design and analysis with application to high speed portable processors and low power wireless communications. He has authored twelve book chapters and many papers in the fields of high speedand low power CMOS design techniques, interconnect and substrate noise, pipelining and retiming, three-dimensional integration, and the theory and application of power and synchronous clock distribution networks. Dr. Friedman has also authored or edited sixteen books, including Clock Distribution Networks in VLSI Circuits and Systems (IEEE Press, 1995), High Performance Clock Distribution Networks (Kluwer Academic Publishers, 1997), Analog Design Issues in Digital VLSI Circuits and Systems (Kluwer Academic Publishers, 1997), Timing Optimization through Clock Skew Scheduling (Kluwer Academic Publishers, 2000 and 2009), On-Chip Inductance in High Speed Integrated Circuits (Kluwer Academic Publishers, 2001), Power Distribution Networks in High Speed Integrated Circuits (Kluwer Academic Publishers, 2004), Multi-Voltage CMOS Circuit Design (John Wiley & Sons Press, 2006), Power Distribution Networks with On-Chip Decoupling Capacitors (Springer Verlag, 2008 and 2011), Three-Dimensional Integrated Circuit Design (Morgan Kaufmann, 2009), and High Performance Integrated Circuit Design (McGraw-Hill Publishers, 2012). Dr. Friedman is a Fellow of the IEEE, Chair of the steering committee for the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, a Regional Editor of the Journal of Circuits, Systems and Computers, a Member of the editorial board of the Analog Integrated Circuits and Signal Processing, Microelectronics Journal, Journal of Low Power Electronics , and Journal of VLSI Signal Processing, and a Member of the technical program committee of a number of conferences. He has been Editor-In-Chief of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, a Distinguished Lecturer of the IEEE CAS Society, a Member of the editorial board of the Proceedings of the IEEE and IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, a member of the IEEE Circuits and Systems (CAS) Society Board of Governors, CAS liaison to the I

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Power Distribution Networks with On-Chip Decoupling Capacitors, 2^nd edition is dedicated to distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. This book provides a broad and cohesive treatment of power distribution systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors. The book provides insight and intuition into the behavior and design of on-chip power distribution systems.

This book has four primary objectives. The first objective is to describe the impedance characteristics of the overall power distribution system, from the voltage regulator through the printed circuit board and package onto the integrated circuit to the terminals of the on-chip circuitry. The second objective is to discuss the inductive characteristics of on-chip power distribution grids and the related circuit behavior of these structures. The third objective is to present design methodologies for efficiently placing on-chip decoupling capacitors in nanoscale integrated circuits. Finally, the fourth objective is to suggest novel architectures for distributing power across an integrated circuit, as well as provide new methodologies to efficiently analyze and design on-chip power grids.

Organized into subareas to provide a more intuitive flow to the reader, this edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of thisadditional material is on managing the complexity of on-chip power distribution networks.