Über die Autorin bzw. den Autor

H. JONATHAN CHAO, PhD, earned his doctorate at The Ohio State University. Since 1992 he has been Professor of Electrical Engineering at Polytechnic University, Brooklyn, New York and conducts research in terabit ATM switches and IP routers, quality of service control, and photonic packet switching. He was co-founder and Chief Technical Officer of Coree Networks Inc., building a terabit IP/MPLS switch router. Between 1985 and 1992 he was a member of technical staff at Telcordia in New Jersey. He is a Fellow of the IEEE and has published widely in the above subjects.
CHEUK H. LAM, PhD, earned his doctorate at the Chinese University of Hong Kong. He is a member of the technical staff at Lucent Technologies Inc., Landover, Maryland.
EIJI OKI, PhD, earned his doctorate at Keio University, Yokohama, Japan. He is a research engineer at NTT Network Service Systems Laboratories, Tokyo. In 2000 he was a visiting scholar at Polytechnic University.

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Complete and comprehensive coverage of packet switching concepts and technologies

The rapid growth of Internet traffic has spurred a new concentration on IP routers and ATM, MPLS, and optical switches. This book addresses the basics, theory, architectures, and technologies for implementing ATM switches and IP routers. It focuses on the architecture for the next generation of broadband switches and routers and provides detailed treatment of both theoretical and practical topics for professionals and students alike.

Broadband Packet Switching Technologies is written with engineers and industry researchers in mind. It describes the basic concepts and fundamentals of ATM switches and IP routers, then divides the switches into different categories. In each category, the authors discuss the operations, problems, strengths, and weaknesses of the switches in performance and implementation. Detailed solutions and algorithms are also provided. The authors also extend fundamental packet-switching concepts to wireless and fiber-optic networks.

Broadband Packet Switching Technologies fills the need for a textbook and reference dedicated to high-speed networking technologies that serves the specific needs of professionals in the telecommunications industry and provides expert material for students in related fields.

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Complete and comprehensive coverage of packet switching concepts and technologies
 
The rapid growth of Internet traffic has spurred a new concentration on IP routers and ATM, MPLS, and optical switches. This book addresses the basics, theory, architectures, and technologies for implementing ATM switches and IP routers. It focuses on the architecture for the next generation of broadband switches and routers and provides detailed treatment of both theoretical and practical topics for professionals and students alike.
 
Broadband Packet Switching Technologies is written with engineers and industry researchers in mind. It describes the basic concepts and fundamentals of ATM switches and IP routers, then divides the switches into different categories. In each category, the authors discuss the operations, problems, strengths, and weaknesses of the switches in performance and implementation. Detailed solutions and algorithms are also provided. The authors also extend fundamental packet-switching concepts to wireless and fiber-optic networks.
 
Broadband Packet Switching Technologies fills the need for a textbook and reference dedicated to high-speed networking technologies that serves the specific needs of professionals in the telecommunications industry and provides expert material for students in related fields.

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Broadband Packet Switching Technologies

John Wiley & Sons

Chapter One

The scalable and distributed nature of the Internet continuously contributes to a wild and rapid growth of its population, including the number of users, hosts, links, and emerging applications. The great success of the Internet thus leads to exponential increases in traffic volumes, stimulating an unprecedented demand for the capacity of the core network.

Network providers therefore face the need of providing a new network infrastructure that can support the growth of traffic in the core network. Advances in fiber throughput and optical transmission technologies have enabled operators to deploy capacity in a dramatic fashion. However, the advancement in packet switch/router technologies is rather slow, so that it is still not able to keep pace with the increase in link transmission speed.

Dense-wavelength-division-multiplexing (DWDM) equipment is installed on each end of the optical fiber to multiplex wavelengths i.e., channels over a single fiber. For example, a 128-channel OC-192 (10 Gbit/s) DWDM system can multiplex the signals to achieve a total capacity of 1.2 Tbit/s. Several vendors are expected to enter trials for wide area DWDM networks that support OC-768 (40 Gbit/s) for each channel in the near future.

Another advanced optical technology that is being deployed in the optical network is the optical cross connect (OXC) system. Since the optical-to-electrical-to-optical conversions do not occur within the system, transmission interfaces are transparent. The OXC System is based on the microelectro-mechanical systems (MEMS) technology, where an array of hundreds or thousands of electrically configurable microscopic mirrors is fabricated on a single substrate to direct light. The switching scheme is based on freely moving mirrors being rotated around micromachined hinges with submillisecond switching speed. It is rate- and format-independent.

As carriers deploy fiber and DWDM equipment to expand capacity, terabit packet switching technologies are required to aggregate high-bit-rate links while achieving higher utilization on the links. Although OXC systems have high-speed interfaces (e.g., 10 or 40 Gbit/s) and large switching capacity (e.g., 10-40 Tbit/s), the granularity of the switching is coarse, e.g., 10 or 40 Gbit/s. As a result, it is required to have high-speed and large-capacity packet switches/routers to aggregate lower-bit-rate traffic to 10 or 40 Gbit/s links. The aggregated traffic can be delivered to destinations through DWDM transmission equipment or OXC systems. The terabit packet switches that are critical elements of the Internet network infrastructure must have switch fabric capable of supporting terabit speeds to eliminate the network bottlenecks. Core terabit switches/routers must also deliver low latency and guaranteed delay variance to support real-time traffic. As a result, quality-of-service (QoS) control techniques, such as traffic shaping, packet scheduling, and buffer management, need to be incorporated into the switches/routers.

Asynchronous transfer mode (ATM) is revolutionizing the telecommunications infrastructure by transmitting integrated voice, data, and video at very high speed. The current backbone network mainly consists of ATM switches and IP routers, where ATM cells and IP packets are carried on an optical physical layer such as the Synchronous Optical Network (SONET). ATM also provides different QoS requirements for various multimedia services. Readers who are interested in knowing the SONET frame structure, the ATM cell format, and the functions associated with SONET/ATM layers are referred to the Appendix.

Along with the growth of the Internet, IP has become the dominant protocol for data traffic and is making inroads into voice transmission as well. Network providers recognize the cost savings and performance advantages of converging voice, data, and video services onto a common network infrastructure, instead of an overlayered structure. Multi-protocol label switching (MPLS) is a new technology combining the advantageous features of the ATM network, short labels and explicit routing, and the connectionless datagram of the IP network. The MPLS network also provides traffic engineering capability to achieve bandwidth provisioning, fast restoration, load balancing, and virtual private network (VPN) services. The so-called label switching routers (LSRs) that route packets can be either IP routers, ATM switches, or frame relay switches. In this book, we will address the issues and technologies of building a scalable switch/router with large capacity, e.g., several terabits per second.

In the rest of this chapter, we briefly describe the ATM network, ATM switch systems, IP router systems, and switch design criteria and performance requirements.

1.1 ATM SWITCH SYSTEMS

1.1.1 Basics of ATM Networks

ATM protocol corresponds to layer 2 as defined in the open systems interconnection (OSI) reference model. ATM is connection-oriented. That is, an end-to-end connection (or virtual channel) needs to be set up before routing ATM cells. Cells are routed based on two important values contained in the 5-byte cell header: the virtual path identifier (VPI) and virtual channel identifier (VCI), where a virtual path consists of a number of virtual channels. The number of bits allocated for a VPI depends on the type of interface. If it is the user network interface (UNI), between the user and the first ATM switch, 8 bits are provided for the VPI. This means that up to [2.sup.8] = 256 virtual paths are available at the user access point. On the other hand, if the it is the network node interface (NNI), between the intermediate ATM switches, 12 bits are provided for the VPI. This indicates that there are [2.sup.12] = 4096 possible virtual paths between ATM switches. In both UNI and NNI, there are 16 bits for the VCI. Thus, there are [2.sup.16] = 65,536 virtual channels for each virtual path.

The combination of the VPI and the VCI determines a specific virtual connection between two ends. Instead of having the same VPI/VCI for the whole routing path, the VPI/VCI is determined on a per-link basis and changes at each ATM switch. Specifically, at each incoming link to a switch node, a VPI/VCI may be replaced with another VPI/VCI at the output link with reference to a table called a routing information table (RIT) in the ATM switch. This substantially increases the possible number of routing paths in the ATM network.

The operation of routing cells is as follows. Each ATM switch has its own RIT containing at least the following fields: old VPI/VCI, new VPI/VCI, output port address, and priority field (optional). When an ATM cell arrives at an input line of the switch, it is split into the 5-byte header and the 48-byte payload. By using the VPI/VCI contained in the header as the old VPI/VCI value, the switch looks in the RIT for the arriving cell's new VPI/VCI. Once the match is found, the old VPI/VCI value is replaced with the new VPI/VCI value. Moreover, the corresponding output port address and priority field are attached to the 48-byte payload of the cell, before it is sent to the switch fabric. The output port address indicates to which output port the cell should be routed. There are three modes of routing operations within the...