Hardware Description Languages : Concepts and Principles

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Über die Autorin bzw. den Autor: Sumit Ghosh is the associate chair for research and graduate programs in the Computer Science and Engineering Department at Arizona State University. Previously, he had been on the faculty at Brown University and has held research positions in private industry. Dr. Ghosh’s research has pioneered work in areas such as preemptive semantics for inertial delays in hardware description languages; execution of VHDL models on distributed processors; behavior-level fault modeling; asynchronous distributed fault simulation; timing verification of asynchronous digital designs; deadlock-free distributed discrete event simulation algorithm (YADDES); dynamically reconfigurable computer architectures; and modeling and large-scale simulation of complex real-world systems. Dr. Ghosh’s additional contributions include a fundamental framework for network security that has been incorporated into the National Security Agency’s Network Rating Model; security on demand in ATM networks; a proposal to integrate the Department of Defense and public ATM network infrastructures; and the synthesis and validation of a comprehensive suite of security attack models for ATM networks. His research is the result of support from the IEEE Foundation, US AFOSR, US Army Research Office, DARPA, Bellcore, NYNEX, National Library of Medicine, NSF, Intel Corp., US Army Research Lab, US Ballistic Missile Defense Organization, National Security Agency, and US Air Force Labs in Rome, New York through Motorola.