Verlag: Springer International Publishing, Springer International Publishing Dez 2007, 2007
ISBN 10: 3031797426 ISBN 13: 9783031797422
Sprache: Englisch
Anbieter: buchversandmimpf2000, Emtmannsberg, BAYE, Deutschland
EUR 29,95
Währung umrechnenAnzahl: 2 verfügbar
In den WarenkorbTaschenbuch. Zustand: Neu. Neuware -Introduction to Logic Synthesis Using Verilog HDL explains how to write accurate Verilog descriptions of digital systems that can be synthesized into digital system netlists with desirable characteristics. The book contains numerous Verilog examples that begin with simple combinational networks and progress to synchronous sequential logic systems. Common pitfalls in the development of synthesizable Verilog HDL are also discussed along with methods for avoiding them. The target audience is anyone with a basic understanding of digital logic principles who wishes to learn how to model digital systems in the Verilog HDL in a manner that also allows for automatic synthesis. A wide range of readers, from hobbyists and undergraduate students to seasoned professionals, will find this a compelling and approachable work. The book provides concise coverage of the material and includes many examples, enabling readers to quickly generate high-quality synthesizable Verilog models.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 84 pp. Englisch.
Verlag: Springer International Publishing, 2007
ISBN 10: 3031797426 ISBN 13: 9783031797422
Sprache: Englisch
Anbieter: AHA-BUCH GmbH, Einbeck, Deutschland
EUR 29,95
Währung umrechnenAnzahl: 1 verfügbar
In den WarenkorbTaschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - Introduction to Logic Synthesis Using Verilog HDL explains how to write accurate Verilog descriptions of digital systems that can be synthesized into digital system netlists with desirable characteristics. The book contains numerous Verilog examples that begin with simple combinational networks and progress to synchronous sequential logic systems. Common pitfalls in the development of synthesizable Verilog HDL are also discussed along with methods for avoiding them. The target audience is anyone with a basic understanding of digital logic principles who wishes to learn how to model digital systems in the Verilog HDL in a manner that also allows for automatic synthesis. A wide range of readers, from hobbyists and undergraduate students to seasoned professionals, will find this a compelling and approachable work. The book provides concise coverage of the material and includes many examples, enabling readers to quickly generate high-quality synthesizable Verilog models.