Anbieter: Romtrade Corp., STERLING HEIGHTS, MI, USA
Zustand: New. This is a Brand-new US Edition. This Item may be shipped from US or any other country as we have multiple locations worldwide.
Anbieter: Romtrade Corp., STERLING HEIGHTS, MI, USA
Zustand: New. This is a Brand-new US Edition. This Item may be shipped from US or any other country as we have multiple locations worldwide.
Anbieter: Romtrade Corp., STERLING HEIGHTS, MI, USA
Zustand: New. This is a Brand-new US Edition. This Item may be shipped from US or any other country as we have multiple locations worldwide.
Verlag: Springer-Verlag New York Inc, 2005
ISBN 10: 0387258701 ISBN 13: 9780387258706
Sprache: Englisch
Anbieter: Revaluation Books, Exeter, Vereinigtes Königreich
EUR 154,01
Anzahl: 2 verfügbar
In den WarenkorbHardcover. Zustand: Brand New. 1st edition. 137 pages. 9.25x6.50x0.75 inches. In Stock.
Taschenbuch. Zustand: Neu. Interconnect Noise Optimization in Nanometer Technologies | Magdy A. Bayoumi (u. a.) | Taschenbuch | xix | Englisch | 2010 | Springer US | EAN 9781441938442 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.
Verlag: Springer US, Springer New York Nov 2005, 2005
ISBN 10: 0387258701 ISBN 13: 9780387258706
Sprache: Englisch
Anbieter: buchversandmimpf2000, Emtmannsberg, BAYE, Deutschland
Buch. Zustand: Neu. Neuware -Interconnect has become the dominating factor in determining system performance in nanometer technologies. Dedicated to this subject, Interconnect Noise Optimization in Nanometer Technologies provides insight and intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits.The authors bring together a wealth of information presenting a range of CAD algorithms and techniques for synthesizing and optimizing interconnect. Practical aspects of the algorithms and the models are explained with sufficient details. The book investigates the most effective parameters in layout optimization. Different post-layout optimization techniques with complexity analysis and benchmarks tests are provided. The impact crosstalk noise and coupling on the wire delay is analyzed. Parameters that affect signal integrity are also considered.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 160 pp. Englisch.
Verlag: Springer, 2005
Sprache: Englisch
Anbieter: Antiquariat Thomas Haker GmbH & Co. KG, Berlin, Deutschland
Verbandsmitglied: GIAQ
EUR 5,92
Anzahl: 1 verfügbar
In den WarenkorbHardcover/Pappeinband. Zustand: Sehr gut. 156 p. Very good. Shrink wrapped. / Sehr guter Zustand. In Folie verschweißt. Sprache: Englisch Gewicht in Gramm: 496.
Anbieter: AHA-BUCH GmbH, Einbeck, Deutschland
Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - Interconnect has become the dominating factor in determining system performance in nanometer technologies. Dedicated to this subject, Interconnect Noise Optimization in Nanometer Technologies provides insight and intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits.The authors bring together a wealth of information presenting a range of CAD algorithms and techniques for synthesizing and optimizing interconnect. Practical aspects of the algorithms and the models are explained with sufficient details. The book investigates the most effective parameters in layout optimization. Different post-layout optimization techniques with complexity analysis and benchmarks tests are provided. The impact crosstalk noise and coupling on the wire delay is analyzed. Parameters that affect signal integrity are also considered.
Verlag: Springer US, Springer New York, 2005
ISBN 10: 0387258701 ISBN 13: 9780387258706
Sprache: Englisch
Anbieter: AHA-BUCH GmbH, Einbeck, Deutschland
Buch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - Presents a range of CAD algorithms and techniques for synthesizing and optimizing interconnectProvides insight & intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits.