Engineering compiler (49 Ergebnisse)

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Zustand: New. *Price HAS BEEN REDUCED by 10% until Monday, Nov. 9 (weekend SALE item)* 334 pp., paperback, NEW!!! - If you are reading this, this item is actually (physically) in our stock and ready for shipment once ordered. We are not bookjackers. Buyer is responsible for any additional duties, taxes, or fees required by recipient's country. …

Engineering a Compiler: Vax-11 Code Generation and Optimization
Patricia Anklam; David Cutler; Jr. Roger Heinen; M. Donald MacLaren
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Engineering a Compiler: Vax-11 Code Generation and Optimization
Patricia Anklam; David Cutler; Jr. Roger Heinen; M. Donald MacLaren
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Engineering a Compiler: Vax-11 Code Generation and Optimization
Patricia Anklam; David Cutler; Jr. Roger Heinen; M. Donald MacLaren
- Hardcover
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Sprache: Englisch
Verlag: Independently Published Jun 2026, 2026
Serie: Buch 1 von 7 - AI Infrastructure, Hardware & Compiler Engineering Series
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Taschenbuch. Zustand: Neu. Neuware - Build Compilers for the AI Hardware FrontierThe explosion of custom AI accelerators-including the Apple Neural Engine, Google TPU, AWS Inferentia, and Qualcomm Hexagon-has created an urgent demand for compiler engineers. These specialists must understand the entire software stack, from neural network graph representation down to hardware-specific code generation. Compiler Engineering for AI Hardware provides the definitive technical foundation for designing, building, and optimizing modern AI compilation pipelines.This hands-on guide bridges the critical gap between high-level machine learning frameworks and low-level hardware design. You will explore real-world compiler architectures and learn how to translate deep learning models into highly efficient machine instructions.What You Will Master- MLIR Architecture: Master multi-level IR design, custom dialect creation, and progressive lowering strategies to LLVM IR.- TVM and Relay/Relax: Leverage TVM, Relax, and MetaSchedule for graph-level optimizations, operator fusion, and auto-tuning.- XLA and PJRT: Understand Google's compiler pipeline, HLO representations, fusion strategies, and hardware runtimes.- Custom Backends: Build custom MLIR dialects and target-specific code generation passes for novel hardware targets.- Memory and Layout Optimizations: Implement memory planning algorithms, loop transformations, and data layout changes to maximize throughput.Whether you are a hardware architect designing next-generation silicon or a software engineer optimizing deep learning inference, this book delivers the practical code examples, IR listings, and architectural insights needed to build production-grade compiler pipelines. Step into the future of systems engineering and master the AI compiler stack today.…

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Taschenbuch. Zustand: Neu. Neuware - Tensor Compiler Engineering is your definitive guide to understanding exactly how machine learning models execute on physical hardware. I wrote this book to completely open the black box of AI infrastructure. It breaks down the complete compilation pipeline-from structuring mathematical computation graphs to generating highly optimized binary files-showing you exactly how to squeeze every drop of performance out of your deployment environment.Imagine you just spent weeks training a massive neural network. The mathematics are perfect. But when you push it to a production server, the latency is terrible, and the system crashes from unexpected Out-of-Memory errors.I have been exactly where you are.For a long time, I struggled to understand why perfectly written code ran so slowly. Then I discovered the truth: the bottleneck was not the math. The bottleneck was how the math was being delivered to the physical processor. I realized that mastering the compiler was the only way to break through this invisible barrier. I spent countless hours mapping out exactly how these systems work, step-by-step, tearing down everything from memory caching to hardware threading. I structured this book so you never have to guess what is happening under the hood of your AI deployments ever again.What's inside- Computation Graph Optimization: Master operator fusion and Multi-Level Intermediate Representation (MLIR) to streamline your math.- Hardware Acceleration: Discover how to manipulate hardware execution using intelligent loop tiling and vector unrolling.- Silicon Real Estate: Learn static versus dynamic memory allocation and how to aggressively recycle physical VRAM buffers.- Backend Code Generation: See exactly how compilers target and write CUDA, ROCm, and bare-metal CPU assembly code.- Production Integration: Seamlessly handle dynamic tensor shapes and debug numerical errors on live servers without crashing.Who it's meant forThis book is written for machine learning engineers, systems developers, and software architects who want to stop relying on bloated software frameworks and start understanding physical execution. If you know how to build a neural network but want to learn how to engineer it to run efficiently on bare silicon, this guide is built for you.The next generation of artificial intelligence belongs to the engineers who control the infrastructure. Do not let hardware limitations choke your software. Grab your copy today and take absolute control of your execution pipeline.…

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Hardcover. Zustand: Good. This entirely revised second edition of Engineering a Compiler is full of technical updates and new material covering the latest developments in compiler technology. In this comprehensive text you will learn important techniques for constructing a modern compiler. Leading educators and researchers Keith Cooper and Linda Torczon combine basic principles with pragmatic insights from their experience building state-of-the-art compilers. They will help you fully understand important techniques such as compilation of imperative and object-oriented languages, construction of static single assignment forms, instruction scheduling, and graph-coloring register allocation.…

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Taschenbuch. Zustand: Neu. Neuware - What if you could understand not just how AI models run-but how the hardware that accelerates them is actually designed How does a neural-network operation become a hardware instruction Why do AI workloads benefit from specialized processors How do processing elements, tensor engines, memory systems, compilers, and programmable hardware work together to create a functioning NPU NPU Engineering from First Principles takes you from these questions to practical NPU system design.Written for beginners while progressing into professional concepts, this book connects AI computation with the hardware and software required to accelerate it. Rather than studying isolated components, you will learn how the complete system fits together-from neural-network mathematics and architecture to implementation and verification.Inside, you will learn how to: - Understand modern AI workloads and NPU architecture- Design processing elements, MAC units, matrix engines, and tensor-processing pipelines- Apply quantization, low-precision computing, sparsity, and model optimization- Build Python reference models and NPU behavioral simulators- Design memory hierarchies, buffers, dataflow, streaming, and double-buffering systems- Create a custom NPU instruction set and assembly language- Understand compiler design, tiling, scheduling, memory allocation, and instruction generation- Develop synthesizable RTL for NPU hardware- Prototype and evaluate NPU designs using FPGA hardware- Verify software, instructions, RTL, and hardware systematically- Understand transformer acceleration, attention processing, KV-cache management, edge AI, and multi-core NPUs- Build 15 practical projects, progressing from individual processing elements to a complete programmable NPU systemBut why does this matter Because designing a successful AI accelerator is not simply about adding more arithmetic units. Performance depends on balancing computation, memory bandwidth, data movement, numerical precision, programmability, and software. This book teaches you to think about those relationships like an accelerator engineer.Are you a student trying to enter AI hardware A programmer wondering what happens beneath AI software An FPGA developer ready for a more ambitious project Or an aspiring processor engineer looking to build practical skills and stronger portfolio projects You don't need to already be an NPU expert. This book starts with the principles and progressively shows you how the pieces connect.So, are you ready to move from simply using AI technology to understanding how its computing engines are built Get your copy of NPU Engineering from First Principles and start developing the skills to model, design, program, verify, and build AI accelerators from the ground up.…

Engineering a Compiler: Vax-11 Code Generation and Optimization
Patricia Anklam; David Cutler; Roger Heinen, Jr.; M. Donald MacLaren
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paperback. Zustand: New. Language:Chinese.Paperback. Publisher: China Machine Press. This book introduces the overview of the compilation. scan. grammar.

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Paperback. Zustand: New. *Textbook and Academic Authors Association (TAA) Textbook Excellence Award Winner, 2024*Engineering a Compiler, Third Edition covers the latest developments in compiler technology, with new chapters focusing on semantic elaboration (the problems that arise in generating code from the ad-hoc syntax-directed translation schemes in a generated parser), on runtime support for naming and addressability, and on code shape for expressions, assignments and control-structures. Leading educators and researchers, Keith Cooper and Linda Torczon, have revised this popular text with a fresh approach to learning important techniques for constructing a modern compiler, combining basic principles with pragmatic insights from their own experience building state-of-the-art compilers.…

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Zustand: New. In English.