defect oriented testing nano metric cmos (9 Ergebnisse)

Zustand: New. Brand New. Soft Cover International Edition. Different ISBN and Cover Image. Priced lower than the standard editions which is usually intended to make them more affordable for students abroad. The core content of the book is generally the same as the standard edition. The country selling restrictions may be printed on the book but is no problem for the self-use. This Item maybe shipped from US or any other country as we have multiple locations worldwide.

Zustand: Sehr gut. Zustand: Sehr gut | Seiten: 352 | Sprache: Englisch | Produktart: Bücher | Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditions and with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. This partitioning choice is actually application dependent.

Zustand: New. In.

Zustand: New. In.

Taschenbuch. Zustand: Neu. Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits | José Pineda de Gyvez (u. a.) | Taschenbuch | xxi | Englisch | 2010 | Humana | EAN 9781441942852 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.

Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditions and with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. This partitioning choice is actually application dependent.

Buch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditions and with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. This partitioning choice is actually application dependent.

Paperback. Zustand: Brand New. 2nd edition. 349 pages. 9.10x6.10x0.90 inches. In Stock.

Hardcover. Zustand: Brand New. 2nd edition. 328 pages. 9.25x6.25x0.75 inches. In Stock.