Correct hardware design verification (34 Ergebnisse)

XII, 482 p. Softcover. Versand aus Deutschland / We dispatch from Germany via Air Mail. Einband bestoßen, daher Mängelexemplar gestempelt, sonst sehr guter Zustand. Imperfect copy due to slightly bumped cover, apart from this in very good condition. Stamped. Lecture Notes in Computer Science, Vol. 2144. Sprache: Englisch. …

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Paperback. Zustand: New. 1993 ed. These proceedings contain the papers presented at theAdvanced Research Working Conference on Correct HardwareDesign Methodologies, held in Arles, France, in May 1993,and organized by the ESPRIT Working Group 6018 CHARME-2andthe Universit de Provence, Marseille, in cooperation withIFIP Working Group 10.2.Formal verification is emerging as a plausible alternativeto exhaustive simulation for establishing correct digitalhardware designs. The validation of functional and timingbehavior is a major bottleneck in current VLSI designsystems, slowing the arrival of products in the marketplacewith its associated increase in cost. From being apredominantly academic area of study until a few years ago,formal design and verification techniques are now beginningto migrate into industrial use. As we are now witnessing anincrease in activity in this area in both academia andindustry, the aim of this working conference was to bringtogether researchers and users from both communities.…

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Paperback. Zustand: New. 2003 ed. This volume contains the proceedings of CHARME 2003, the12th Advanced - search Working Conference on Correct Hardware Design and Veri?cation - thods. CHARME 2003 continues the series of working conferences devoted to the development and use of leading-edge formal techniques and tools for the design and veri?cation of hardware and hardware-like systems. Previous events in the 'CHARME' series were held in Edinburgh (2001), Bad Herrenalb (1999), Montreal (1997), Frankfurt (1995), Arles (1993) and - rin (1991). This series of meetings were organized in cooperation with IFIP WG 10.5and10.2.Priormeetings,stretchingbacktotheearliestdaysofformalha- wareveri?cationwereheldundervariousnamesinMiami(1990),Leuven(1989), Glasgow (1988), Grenoble (1986), Edinburgh (1985) and Darmstadt (1984). We now have a well-established convention whereby the European CHARME con- rence alternates with its biennial counterpart, the International Conference on Formal Methods in Computer-Aided Design(FMCAD),whichisheldinev- numbered years in the USA. CHARME 2003 took place during 21-24 October 2003 at the Computer Science Department of the University of L'Aquila, Italy.It was cosponsored by the IFIP TC10/WG10 Working Group on Design and Engineering of Electronic Systems. The CHARME 2003 scienti?c program was comprised of: - A morning Tutorial by Daniel Geist aimed at industrial and academic - terchange. - Two Invited Lectures by Wolfgang Roesner and Fabio Somenzi. - Regular Sessions, featuring 24 papers selected out of 65 submissions, r- ging from foundational contributions to tool presentations. - Short Presentations, featuring 8 short contributions accompanied by a short presentation. The conference, of course, also included informal tool demonstrations, not announced in the o?cial program.…

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Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - Invited Talks.- Is Formal Verification Bound to Remain a Junior Partner of Simulation .- Verification Challenges in Configurable Processor Design with ASIP Meister.- Tutorial.- Towards the Pervasive Verification of Automotive Systems.- Functional Approaches to Design Description.- Wired: Wire-Aware Circuit Design.- Formalization of the DE2 Language.- Game Solving Approaches.- Finding and Fixing Faults.- Verifying Quantitative Properties Using Bound Functions.- Abstraction.- How Thorough Is Thorough Enough .- Interleaved Invariant Checking with Dynamic Abstraction.- Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units.- Algorithms and Techniques for Speeding (DD-Based) Verification 1.- Efficient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting.- Achieving Speedups in Distributed Symbolic Reachability Analysis Through Asynchronous Computation.- Saturation-Based Symbolic Reachability Analysis Using Conjunctive and Disjunctive Partitioning.- Real Time and LTL Model Checking.- Real-Time Model Checking Is Really Simple.- Temporal Modalities for Concisely Capturing Timing Diagrams.- Regular Vacuity.- Algorithms and Techniques for Speeding Verification 2.- Automatic Generation of Hints for Symbolic Traversal.- Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies.- A New SAT-Based Algorithm for Symbolic Trajectory Evaluation.- Evaluation of SAT-Based Tools.- An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment.- Model Reduction.- Exploiting Constraints in Transformation-Based Verification.- Identification and Counter Abstraction for Full Virtual Symmetry.- Verification of Memory Hierarchy Mechanisms.- On the Verificationof Memory Management Mechanisms.- Counterexample Guided Invariant Discovery for Parameterized Cache Coherence Verification.- Short Papers.- Symbolic Partial Order Reduction for Rule Based Transition Systems.- Verifying Timing Behavior by Abstract Interpretation of Executable Code.- Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths.- Deadlock Prevention in the Æthereal Protocol.- Acceleration of SAT-Based Iterative Property Checking.- Error Detection Using BMC in a Parallel Environment.- Formal Verification of Synchronizers.- A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems.- Improvements to the Implementation of Interpolant-Based Model Checking.- High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design.- Proving Parameterized Systems: The Use of Pseudo-Pipelines in Polyhedral Logic.- Resolving Quartz Overloading.- FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers.- Predictive Reachability Using a Sample-Based Approach.- Minimizing Counterexample of ACTL Property.- Data Refinement for Synchronous System Specification and Construction.- Introducing Abstractions via Rewriting.- A Case Study: Formal Verification of Processor Critical Properties.…

Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - CHARME'99 is the tenth in a series of working conferences devoted to the dev- opment and use of leading-edge formal techniques and tools for the design and veri cation of hardware and systems. Previous conferences have been held in Darmstadt (1984), Edinburgh (1985), Grenoble (1986), Glasgow (1988), Leuven (1989), Torino (1991), Arles (1993), Frankfurt (1995) and Montreal (1997). This workshop and conference series has been organized in cooperation with IFIP WG 10. 5. It is now the biannual counterpart of FMCAD, which takes place every even-numbered year in the USA. The 1999 event took place in Bad Her- nalb, a resort village located in the Black Forest close to the city of Karlsruhe. The validation of functional and timing behavior is a major bottleneck in current VLSI design systems. A predominantly academic area of study until a few years ago, formal design and veri cation techniques are now migrating into industrial use. The aim of CHARME'99 is to bring together researchers and users from academia and industry working in this active area of research. Two invited talks illustrate major current trends: the presentation by G erard Berry (Ecole des Mines de Paris, Sophia-Antipolis, France) is concerned with the use of synchronous languages in circuit design, and the talk given by Peter Jansen (BMW, Munich, Germany) demonstrates an application of formal methods in an industrial environment. The program also includes 20 regular presentations and 12 short presentations/poster exhibitions that have been selected from the 48 submitted papers.…

Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - This volume contains the proceedings of CHARME 2001, the Eleventh Advanced Research Working Conference on Correct Hardware Design and Veri cation Methods. CHARME 2001 is the 11th in a series of working conferences devoted to the development and use of leading-edge formal techniques and tools for the design and veri cation of hardware and hardware-like systems. Previous events in the 'CHARME' series were held in Bad Herrenalb (1999), Montreal (1997), Frankfurt (1995), Arles (1993), and Torino (1991). This series of meetings has been organized in cooperation with IFIP WG 10.5 and WG 10.2. Prior meetings, stretching backto the earliest days of formal hardware veri cation, were held under various names in Miami (1990), Leuven (1989), Glasgow (1988), Grenoble (1986), Edinburgh (1985), and Darmstadt (1984). The convention is now well-established whereby the European CHARME conference alternates with its biennial counterpart, the International Conference on Formal Methods in Computer-Aided Design (FMCAD), which is held on even-numbered years in the USA. The conference tookplace during 4-7 September 2001 at the Institute for System Level Integration in Livingston, Scotland. It was co-hosted by the - stitute and the Department of Computing Science of Glasgow University and co-sponsored by the IFIP TC10/WG10.5 Working Group on Design and En- neering of Electronic Systems. CHARME 2001 also included a scienti c session and social program held jointly with the 14th International Conference on Th- rem Proving in Higher Order Logics (TPHOLs), which was co-located in nearby Edinburgh.…

Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - Invited Talks.- What Is beyond the RTL Horizon for Microprocessor and System Design .- The Charme of Abstract Entities.- Tutorial.- The PSL/Sugar Specification Language A Language for all Seasons.- Software Verification.- Finding Regularity: Describing and Analysing Circuits That Are Not Quite Regular.- Predicate Abstraction with Minimum Predicates.- Efficient Symbolic Model Checking of Software Using Partial Disjunctive Partitioning.- Processor Verification.- Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP.- A Hazards-Based Correctness Statement for Pipelined Circuits.- Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT.- Automata Based Methods.- On Complementing Nondeterministic Büchi Automata.- Coverage Metrics for Formal Verification.- 'More Deterministic' vs. 'Smaller' Büchi Automata for Efficient LTL Model Checking.- Short Papers 1.- An Optimized Symbolic Bounded Model Checking Engine.- Constrained Symbolic Simulation with Mathematica and ACL2.- Semi-formal Verification of Memory Systems by Symbolic Simulation.- CTL May Be Ambiguous When Model Checking Moore Machines.- Specification Methods.- Reasoning about GSTE Assertion Graphs.- Towards Diagrammability and Efficiency in Event Sequence Languages.- Executing the Formal Semantics of the Accellera Property Specification Language by Mechanised Theorem Proving.- Protocol Verification.- On Combining Symmetry Reduction and Symbolic Representation for Efficient Model Checking.- On the Correctness of an Intrusion-Tolerant Group Communication Protocol.- Exact and Efficient Verification of Parameterized Cache Coherence Protocols.- Short Papers 2.- Design and Implementation of an Abstract Interpreter for VHDL.- A ProgrammingLanguage Based Analysis of Operand Forwarding.- Integrating RAM and Disk Based Verification within the Mur Verifier.- Design and Verification of CoreConnectTM IP Using Esterel.- Theorem Proving.- Inductive Assertions and Operational Semantics.- A Compositional Theory of Refinement for Branching Time.- Linear and Nonlinear Arithmetic in ACL2.- Bounded Model Checking.- Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking.- Convergence Testing in Term-Level Bounded Model Checking.- The ROBDD Size of Simple CNF Formulas.- Model Checking and Application.- Efficient Hybrid Reachability Analysis for Asynchronous Concurrent Systems.- Finite Horizon Analysis of Markov Chains with the Mur Verifier.- Improved Symbolic Verification Using Partitioning Techniques.…

Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book constitutes the refereed proceedings of the IFIP WG10.5 Advanced Research Working Conference on Correct Hardware Design Methodologies, CHARME '95, held in Frankfurt, Germany, in October 1995.The 20 revised full papers presented were carefully selected by the program committee and address all current aspects of research and advanced applications in the field of formal verification of hardware. Among the topics covered are model checking, theorem proving, formally verified synthesis, process algebras, finite state systems, verification environments, language containment, and VHDL.…

Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - These proceedings contain the papers presented at theAdvanced Research Working Conference on Correct HardwareDesign Methodologies, held in Arles, France, in May 1993,and organized by the ESPRIT Working Group 6018 CHARME-2andthe Universit de Provence, Marseille, in cooperation withIFIP Working Group 10.2.Formal verification is emerging as a plausible alternativeto exhaustive simulation for establishing correct digitalhardware designs. The validation of functional and timingbehavior is a major bottleneck in current VLSI designsystems, slowing the arrival of products in the marketplacewith its associated increase in cost. From being apredominantly academic area of study until a few years ago,formal design and verification techniques are now beginningto migrate into industrial use. As we are now witnessing anincrease in activity in this area in both academia andindustry, the aim of this working conference was to bringtogether researchers and users from both communities.…

Softcover. Zustand: Gut. Gebraucht - Gut Zustand: Gut, Mängelexemplar, XII, 426 p. Also available online. About this book: his book constitutes the refereed proceedings of the 12th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods, CHARME 2003, held in L'Aquila, Italy in October 2003. The 24 revised full papers and 8 short papers presented were carefully reviewed and selected from 65 submissions. The papers are organized in topical sections on software verification, automata based methods, processor verification, specification methods, theorem proving, bounded model checking, and model checking and applications. Written for researchers and professionals. …

Taschenbuch. Zustand: Neu. Correct Hardware Design and Verification Methods | IFIP WG 10.2 Advanced Research Working Conference, CHARME'93, Arles, France, May 24-26, 1993. Proceedings | George J. Milne (u. a.) | Taschenbuch | ix | Englisch | 1993 | Springer | EAN 9783540567783 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.…

Taschenbuch. Zustand: Neu. Correct Hardware Design and Verification Methods | 13th IFIP WG 10.5Advanced Research, Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings | Dominique Borrione (u. a.) | Taschenbuch | xii | Englisch | 2005 | Springer | EAN 9783540291053 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.…

Taschenbuch. Zustand: Neu. Correct Hardware Design and Verification Methods | 10th IFIP WG10.5 Advanced Research Working Conference, CHARME'99, Bad Herrenalb, Germany, September 27-29, 1999, Proceedings | Laurence Pierre (u. a.) | Taschenbuch | xii | Englisch | 1999 | Springer | EAN 9783540665595 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.…

Taschenbuch. Zustand: Neu. Correct Hardware Design and Verification Methods | 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003, Proceedings | Daniel Geist (u. a.) | Taschenbuch | Einband - flex.(Paperback) | Englisch | 2003 | Springer | EAN 9783540203636 | Verantwortliche Person für die EU: Springer Nature Customer Service Center GmbH, Europaplatz 3, 69115 Heidelberg, productsafety[at]springernature[dot]com | Anbieter: preigu.…

Paperback. Zustand: New. 1993 ed. These proceedings contain the papers presented at theAdvanced Research Working Conference on Correct HardwareDesign Methodologies, held in Arles, France, in May 1993,and organized by the ESPRIT Working Group 6018 CHARME-2andthe Universit de Provence, Marseille, in cooperation withIFIP Working Group 10.2.Formal verification is emerging as a plausible alternativeto exhaustive simulation for establishing correct digitalhardware designs. The validation of functional and timingbehavior is a major bottleneck in current VLSI designsystems, slowing the arrival of products in the marketplacewith its associated increase in cost. From being apredominantly academic area of study until a few years ago,formal design and verification techniques are now beginningto migrate into industrial use. As we are now witnessing anincrease in activity in this area in both academia andindustry, the aim of this working conference was to bringtogether researchers and users from both communities.…