Isbn: 9789811010729 - high-level estimation and exploration of reliability for multi-processor system-on-chip (computer architecture and design methodologies) (4 Ergebnisse)

Zustand: New. In.

Zustand: New.

Hardcover. Zustand: Brand New. 217 pages. 9.25x6.10x0.56 inches. In Stock.

Buch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.…