Isbn: 9780123739735 - system-on-chip test architectures: nanometer design for testability (volume .) (systems on silicon, volume .) (3 Ergebnisse)

Zustand: New. A guide to VLSI Testing and Design-for-Testability techniques that allows students, researchers, DFT practitioners, and VLSI designers to master System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. It also includes practical problems at the end of each chapter for students. Series: Systems on Silicon. Num Pages: 896 pages, Approx. 600 illustrations. BIC Classification: THR. Category: (P) Professional & Vocational. Dimension: 242 x 199 x 38. Weight in Grams: 1602. . 2007. 1st Edition. hardcover. . . . . Books ship from the US and Ireland.…

Zustand: New. Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (.

Hardcover. Zustand: Brand New. illustrated edition. 896 pages. 9.50x7.50x1.50 inches. In Stock.