Strojwas andrzej (12 Ergebnisse)
Sprache: Englisch
Verlag: Kluwer Academic Publishers, Dordrecht, Holland, 1997
- Hardcover
- Erstausgabe
Anbieter: PsychoBabel & Skoob Books, Didcot, Vereinigtes KönigreichPsychoBabel & Skoob Books
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Gebraucht - Gut
EUR 32,15
EUR 14,59 VersandVersand von Vereinigtes Königreich nach USAAnzahl: 1 verfügbar
hardcover. Zustand: Very Good. No Dust Jacket. First Edition. Hardback in very good condition. Printed boards, a little scuffed; previous owner's name on FEP, no jacket as issued; contents clean, sound, bright. TPW. Used.
- Softcover
Anbieter: Ria Christie Collections, Uxbridge, Vereinigtes KönigreichRia Christie Collections
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Neu
EUR 116,46
EUR 13,98 VersandVersand von Vereinigtes Königreich nach USAAnzahl: Mehr als 20 verfügbar
Zustand: New. In.
- Hardcover
Anbieter: Ria Christie Collections, Uxbridge, Vereinigtes KönigreichRia Christie Collections
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Neu
EUR 116,46
EUR 13,98 VersandVersand von Vereinigtes Königreich nach USAAnzahl: Mehr als 20 verfügbar
Zustand: New. In.
- Hardcover
Anbieter: Buchpark, Trebbin, DeutschlandBuchpark
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Gebraucht - Gut
EUR 35,62
EUR 105,00 VersandVersand von Deutschland nach USAAnzahl: 1 verfügbar
Zustand: Gut. Zustand: Gut | Sprache: Englisch | Produktart: Bücher | Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre-fa…brication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
- Hardcover
Anbieter: Kennys Bookstore, Olney, MD, USAKennys Bookstore
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Neu
EUR 168,50
EUR 9,23 VersandVersand innerhalb von USAAnzahl: 15 verfügbar
Zustand: New. This text applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. Num Pages: 155 pages, bio…graphy. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 11. Weight in Grams: 426. . 1997. Hardback. . . . . Books ship from the US and Ireland.
VLSI Design for Manufacturing: Yield Enhancement (The Springer International Series in Engineering and Computer Science)
Director, Stephen W. W.; Maly, Wojciech; Strojwas, Andrzej J.
- Softcover
Anbieter: Ria Christie Collections, Uxbridge, Vereinigtes KönigreichRia Christie Collections
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Neu
EUR 165,70
EUR 13,98 VersandVersand von Vereinigtes Königreich nach USAAnzahl: Mehr als 20 verfügbar
Zustand: New. In.
- Hardcover
Anbieter: Ria Christie Collections, Uxbridge, Vereinigtes KönigreichRia Christie Collections
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Neu
EUR 165,70
EUR 13,98 VersandVersand von Vereinigtes Königreich nach USAAnzahl: Mehr als 20 verfügbar
Zustand: New. In.
- Hardcover
Anbieter: AHA-BUCH GmbH, Einbeck, DeutschlandAHA-BUCH GmbH
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Neu
EUR 112,77
EUR 62,18 VersandVersand von Deutschland nach USAAnzahl: 1 verfügbar
Buch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre…-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
- Softcover
Anbieter: Buchpark, Trebbin, DeutschlandBuchpark
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Gebraucht - Sehr gut
EUR 81,18
EUR 105,00 VersandVersand von Deutschland nach USAAnzahl: 1 verfügbar
Zustand: Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher | Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research…in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
- Hardcover
Anbieter: moluna, Greven, Deutschlandmoluna
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Neu
EUR 180,97
EUR 48,99 VersandVersand von Deutschland nach USAAnzahl: Mehr als 20 verfügbar
Gebunden. Zustand: New. One of the keys to success in the IC industry is getting a new product to market in a timely fashion and being able to produce that product with sufficient yield to be profitable. There are two ways to increase yield: by improving the control of the manufac.
- Hardcover
Anbieter: Kennys Bookstore, Olney, MD, USAKennys Bookstore
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenZustand: Neu
EUR 256,84
EUR 9,23 VersandVersand innerhalb von USAAnzahl: 15 verfügbar
Zustand: New. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 292 pages, biography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 234 x 156 x 19. Weight in Grams: 609. . 1989. Hardback. . . . . Books ship from the U…S and Ireland.
- Hardcover
Anbieter: Celler Versandantiquariat, Eicklingen, DeutschlandCeller Versandantiquariat
Verkäufer/-in kontaktierenVerkäufer/-in mit 5 SternenVerbandsmitglied: GIAQ
Zustand: Gebraucht
EUR 26,00
EUR 38,00 VersandVersand von Deutschland nach USAAnzahl: 1 verfügbar
Kluwer, Boston, 1990. XII, 291 pages with some graphics, hardcover, (former library book)--- 750 Gramm.
