Harold grubin (8 Ergebnisse)

Zustand: Gut. Zustand: Gut | Sprache: Englisch | Produktart: Bücher | Keine Beschreibung verfügbar.

Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - The past three decades have been a period where useful current and voltage instabilities in solids have progressed from exciting research problems to a wide variety of commercially available devices. Materials and electronics research has led to devices such as the tunnel (Esaki) diode, transferred electron (Gunn) diode, avalanche diodes, real-space transfer devices, and the like. These structures have proven to be very important in the generation, amplification, switching, and processing of microwave signals up to frequencies exceeding 100 GHz. In this treatise we focus on a detailed theoretical understanding of devices of the kind that can be made unstable against circuit oscillations, large amplitude switching events, and in some cases, internal rearrangement of the electric field or current density distribution. The book is aimed at the semiconductor device physicist, engineer, and graduate student. A knowledge of solid state physics on an elementary or introductory level is assumed. Furthermore, we have geared the book to device engineers and physicists desirous of obtaining an understanding substantially deeper than that associated with a small signal equivalent circuit approach. We focus on both analytical and numerical treatment of specific device problems, concerning ourselves with the mechanism that determines the constitutive relation governing the device, the boundary conditions (contact effects), and the effect of the local circuit environment.…

Paperback. Zustand: Brand New. reprint edition. 480 pages. 9.25x6.10x1.09 inches. In Stock.

Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - The operation of semiconductor devices depends upon the use of electrical potential barriers (such as gate depletion) in controlling the carrier densities (electrons and holes) and their transport. Although a successful device design is quite complicated and involves many aspects, the device engineering is mostly to devise a 'best' device design by defIning optimal device structures and manipulating impurity profIles to obtain optimal control of the carrier flow through the device. This becomes increasingly diffIcult as the device scale becomes smaller and smaller. Since the introduction of integrated circuits, the number of individual transistors on a single chip has doubled approximately every three years. As the number of devices has grown, the critical dimension of the smallest feature, such as a gate length (which is related to the transport length defIning the channel), has consequently declined. The reduction of this design rule proceeds approximately by a factor of 1. 4 each generation, which means we will be using 0. 1-0. 15 ). lm rules for the 4 Gb chips a decade from now. If we continue this extrapolation, current technology will require 30 nm design rules, and a cell 3 2 size 10 nm , for a 1Tb memory chip by the year 2020. New problems keep hindering the high-performance requirement. Well-known, but older, problems include hot carrier effects, short-channel effects, etc. A potential problem, which illustrates the need for quantum transport, is caused by impurity fluctuations.…

Gebunden. Zustand: New. Proceedings of a NATO ASI held in Il Ciocco, Italy, July 17-30, 1994 The operation of semiconductor devices depends upon the use of electrical potential barriers (such as gate depletion) in controlling the carrier densities (electrons and holes) an.

Paperback. Zustand: Brand New. reprint edition. 744 pages. 9.26x6.11x1.57 inches. In Stock.

Buch. Zustand: Neu. Neuware - The operation of semiconductor devices depends upon the use of electrical potential barriers (such as gate depletion) in controlling the carrier densities (electrons and holes) and their transport. Although a successful device design is quite complicated and involves many aspects, the device engineering is mostly to devise a 'best' device design by defIning optimal device structures and manipulating impurity profIles to obtain optimal control of the carrier flow through the device. This becomes increasingly diffIcult as the device scale becomes smaller and smaller. Since the introduction of integrated circuits, the number of individual transistors on a single chip has doubled approximately every three years. As the number of devices has grown, the critical dimension of the smallest feature, such as a gate length (which is related to the transport length defIning the channel), has consequently declined. The reduction of this design rule proceeds approximately by a factor of 1. 4 each generation, which means we will be using 0. 1-0. 15 ). lm rules for the 4 Gb chips a decade from now. If we continue this extrapolation, current technology will require 30 nm design rules, and a cell 3 2 size 10 nm , for a 1Tb memory chip by the year 2020. New problems keep hindering the high-performance requirement. Well-known, but older, problems include hot carrier effects, short-channel effects, etc. A potential problem, which illustrates the need for quantum transport, is caused by impurity fluctuations.…

Zustand: As New. Unread book in perfect condition.