Bertacco valeria (17 Ergebnisse)

Zustand: New. In English.

Zustand: New. This is a Brand-new US Edition. This Item may be shipped from US or any other country as we have multiple locations worldwide.

Zustand: Gebraucht / Used. Fine state d577e.

Paperback. Zustand: Brand New. 2013 edition. 376 pages. 9.20x6.10x1.00 inches. In Stock.

Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book constitutes the refereed proceedings of the 9th International Haifa Verification Conference, HVC 2013, held in Haifa, Israel in November 2013. The 24 revised full papers presented were carefully reviewed and selected from 49 submissions. The papers are organized in topical sections on SAT and SMT-based verification, software testing, supporting dynamic verification, specification and coverage, abstraction and model presentation.…

Taschenbuch. Zustand: Neu. Hardware and Software: Verification and Testing | 9th International Haifa Verification Conference, HVC 2013, Haifa, Israel, November 5-7, 2013, Proceedings | Valeria Bertacco (u. a.) | Taschenbuch | Lecture Notes in Computer Science | xx | Englisch | 2013 | Springer | EAN 9783319030760 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.…

Zustand: New. In English.

Zustand: New. In English.

Buch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - Scalable Hardware Verification with Symbolic Simulation presents recent advancements in symbolic simulation-based solutions which radically improve scalability. It overviews current verification techniques, both based on logic simulation and formal verification methods, and unveils the inner workings of symbolic simulation. The core of this book focuses on new techniques that narrow the performance gap between the complexity of digital systems and the limited ability to verify them. In particular, it covers a range of solutions that exploit approximation and parametrization methods, including quasi-symbolic simulation, cycle-based symbolic simulation, and parameterizations based on disjoint-support decompositions.In structuring this book, the author's hope was to provide interesting reading for a broad range of design automation readers. The first two chapters provide an overview of digital systems design and, in particular, verification. Chapter 3 reviews mainstream symbolic techniques in formal verification, dedicating most of its focus to symbolic simulation. The fourth chapter covers the necessary principles of parametric forms and disjoint-support decompositions. Chapters 5 and 6 focus on recent symbolic simulation techniques, and the final chapter addresses key topics needing further research.Scalable Hardware Verification with Symbolic Simulation is for verification engineers and researchers in the design automation field.Highlights:A discussion of the leading hardware verification techniques, including simulation and formal verification solutionsImportant concepts related to the underlying models and algorithms employed in the fieldThe latest innovations in the area of symbolic simulation, exploiting techniques such as parametric forms and decomposition properties of BooleanfunctionsProviding insights into possible new developments in the hardware verification.…

Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - Scalable Hardware Verification with Symbolic Simulation presents recent advancements in symbolic simulation-based solutions which radically improve scalability. It overviews current verification techniques, both based on logic simulation and formal verification methods, and unveils the inner workings of symbolic simulation. The core of this book focuses on new techniques that narrow the performance gap between the complexity of digital systems and the limited ability to verify them. In particular, it covers a range of solutions that exploit approximation and parametrization methods, including quasi-symbolic simulation, cycle-based symbolic simulation, and parameterizations based on disjoint-support decompositions.In structuring this book, the author's hope was to provide interesting reading for a broad range of design automation readers. The first two chapters provide an overview of digital systems design and, in particular, verification. Chapter 3 reviews mainstream symbolic techniques in formal verification, dedicating most of its focus to symbolic simulation. The fourth chapter covers the necessary principles of parametric forms and disjoint-support decompositions. Chapters 5 and 6 focus on recent symbolic simulation techniques, and the final chapter addresses key topics needing further research.Scalable Hardware Verification with Symbolic Simulation is for verification engineers and researchers in the design automation field.Highlights:A discussion of the leading hardware verification techniques, including simulation and formal verification solutionsImportant concepts related to the underlying models and algorithms employed in the fieldThe latest innovations in the area of symbolic simulation, exploiting techniques such as parametric forms and decomposition properties of BooleanfunctionsProviding insights into possible new developments in the hardware verification.…

Hardcover. Zustand: Brand New. 1st edition. 180 pages. 9.25x6.25x0.50 inches. In Stock.

Zustand: New. In English.

Paperback. Zustand: Brand New. 200 pages. 9.50x6.50x0.46 inches. In Stock.

Zustand: New. In English.

Zustand: New. In English.

Zustand: New. In English.

Buch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - Functional Design Errors in Digital Circuits Diagnosis covers a wide spectrum of innovative methods to automate the debugging process throughout the design flow: from Register-Transfer Level (RTL) all the way to the silicon die. In particular, this book describes: (1) techniques for bug trace minimization that simplify debugging; (2) an RTL error diagnosis method that identifies the root cause of errors directly; (3) a counterexample-guided error-repair framework to automatically fix errors in gate-level and RTL designs; (4) a symmetry-based rewiring technology for fixing electrical errors; (5) an incremental verification system for physical synthesis; and (6) an integrated framework for post-silicon debugging and layout repair. The solutions provided in this book can greatly reduce debugging effort, enhance design quality, and ultimately enable the design and manufacture of more reliable electronic devices.…