Verilogb. QuickStart: A Practical Guide to Simulation and Synthesis in Verilog

This work has been revised and updated in accordance with the new IEEE 1364-1999 standard, much of which applies to synthesizable Verilog. New examples have been included as well as additional material added throughout. It focuses on the most commonly used elements of the Verilog Hardware Description Language used by designers for simulation and synthesis of ASICS and FPGAs. It makes learning Verilog easy by following a well proven approach used in the author's classes for many years. The book is a basic, practical, introductory textbook for professionals and students alike. It explains how a designer can be more effective through the use of the Verilog Hardware Description Language to simulate and document a design. It also presents some of the formal Verilog syntax and definitions and then shows practical uses. This book does not oversimplify the Verilog language nor does it emphasize theory. The text has over 100 examples that are used to illustrate aspects of the language. The later chapters focus on working with modelling style and explaining why and when one would use different elements of the language. Another feature of the book is the chapter on state machine modelling. There is a chapter on test benches and testing strategy as well as a chapter on debugging. It is designed to teach the Verilog language, to show the designer how to model in Verilog and to explain the basics of using Verilog simulators. The accompanying disk contains over 100 runable Verilog examples from the book.