This is an ex-library book and may have the usual library/used-book markings inside.This book has hardback covers. In good all round condition. No dust jacket. Disk missing. Please note the Image in this listing is a stock photo and may not match the covers of the actual item,750grams, ISBN:9783540600329.

Bestandsnummer des Verk�ufers 5834200

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Bibliografische Details

Titel

VLSI Chip Design With the Hardware Description Language VERILOG: An Introduction Based on a Large RISC Processor Design

Verlag

Springer-Verlag Berlin And Heidelberg Gmbh & Co. K

Erscheinungsjahr

1996

Sprache

Englisch

ISBN-10

3540600329

ISBN-13

9783540600329

Einband

Hardcover

Zustand

Good

Verk�uferkataloge

Engineering

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Inhaltsangabe

The art of transforming a circuit idea into a chip has changed permanently. Formerly, the electrical, physical and geometrical tasks were predominant. Later, mainly net lists of gates had to be constructed. Nowadays, hardware description languages (HDL) similar to programming languages are central to digital circuit design. HDL-based design is the main subject of this book. After emphasizing the economic importance of chip design as a key technology, the book deals with VLSI design (Very Large Scale Integration), the design of modern RISC processors, the hardware description language VERILOG, and typical modeling techniques. Numerous examples as well as a VERILOG training simulator are included on a disk.

Von der hinteren Coverseite

This book introduces to modern design of large chips. A powerful RISC processor in the range of a SPARC is apecified in a hardware description language (HDL), it is developed hierarchically and is finally sent as a gate model to the silicon vendor LSI Logic for production. The resulting processor on a semi-custom gate-array chip with more than 50.000 used gates and an efficiency of up to 40 MIPS is tested on an automatic test equipment and a testboard. The book also introduces thoroughly to the HDL VERILOG. The included disk contains more than 40 small and medium sized executable VERILOG examples, the large processor models and the VERILOG simulator VeriWell running on PC or SPARC.

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