Optimization of Electrical Parameters (CNTFET). Dieser Artikel ist nicht verfügbar.
Sprache: Englisch
Verlag: LAP LAMBERT Academic Publishing, 2025
- Softcover
- Neu

Anbieter: PBShop.store US, Wood Dale, IL, USAPBShop.store US
Verkäufer/-in mit 5 Sternen
Verkäufer:in bei ZVAB seit 7. April 2005
Nicht verfügbar
Softcover
Zustand: Neu
EUR 49,78
Artikelbeschreibung des Verkäufers
New Book. Shipped from UK. Established seller since 2000.
Bestandsnummer des Verkäufers L2-9786138263340
- Titel
- Optimization of Electrical Parameters (CNTFET)
- Autor
- Pal, Krishna
- Verlag
- LAP LAMBERT Academic Publishing
- Erscheinungsjahr
- 2025
- Zustand
- New
- Einband
- PAP
- Sprache
- Englisch
- ISBN-10
- 6138263340
- ISBN-13
- 9786138263340
- Artikelgewicht
- 104 Gramm
In the sector of electronics, the demand for technological improvement has been steadilyincreasing. Until now, silicon has been the most popular material for addressing currentdemands. However, silicon has its own set of limits; silicon-based integrated circuits andthe scaling of silicon MOSFET design confront issues such as tunnelling effect, gate oxidethickness impact, and so on, which has prompted the development of alternative materials.The expanding academic interest in carbon nanotubes (CNTs) as a possible new type ofelectronic material has resulted in substantial advances in CNT physics, including ballisticand non-ballistic electron transport properties. Low bias transport in a nanotube can benearly ballistic across distances of several hundred nanometers. Extended circuit-levelmodels that can capture both ballistic and non-ballistic electron transport phenomena,including elastic, phonon scattering, strain, and tunnelling effects, have been created fornon-ballistic CNT transistors. The effect of gate oxide thickness on the performance ofnon-ballistic CNTFETs was investigated in our results section.
„Inhaltsangabe“ gehört möglicherweise zu einer anderen Auflage dieses Titels.
Über die Autorin bzw. den Autor
Krishna Pal received the M.Tech degree from Malaviya National Institute of Technology (MNIT) Jaipur, in 2021 and currently working as a PhD scholar at Indian Institute of Information Technology Sri City in the area of VLSI Design.
„Über diesen Titel“ gehört möglicherweise zu einer anderen Auflage dieses Titels.