Welcome to the proceedings of PATMOS 2008, the 18th in a series of int- national workshops. PATMOS 2008 was organized by INESC-ID / IST - TU Lisbon, Portugal, with sponsorship by Cadence, IBM, Chipidea, and Tecmic, and technical co-sponsorship by the IEEE. Over the years, PATMOS has evolved into an important European event, where researchers from both industry and academia discuss and investigate the emerging challenges in future and contemporary applications, design meth- ologies, and tools required for the development of the upcoming generations of integrated circuits and systems. The technical program of PATMOS 2008 c- tained state-of-the-art technical contributions, three invited talks, and a special session on recon?gurable architectures. The technical program focused on t- ing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and op- mization in the nanometer era. The Technical Program Committee, with the assistance of additional expert reviewers, selected the 41 papers presented at PATMOS. The papers were - ganized into 7 oral sessions (with a total of 31 papers) and 2 poster sessions (with a total of 10 papers). As is customary for the PATMOS workshops, full papers were required for review, and a minimum of three reviews were received per manuscript.

Von der hinteren Coverseite:

This book constitutes the thoroughly refereed post-conference proceedings of 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008, featuring Integrated Circuit and System Design, held in Lisbon, Portugal during September 10-12, 2008.

The 31 revised full papers and 10 revised poster papers presented together with 3 invited talks and 4 papers from a special session on reconfigurable architectures were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-leakage and subthreshold circuits, low-power methods and models, arithmetic and memories, variability and statistical timing, synchronization and interconnect, power supplies and switching noise, low-power circuits; reconfigurable architectures, circuits and methods, power and delay modeling, as well as power optimizations addressing reconfigurable architectures.

��ber diesen Titel� kann sich auf eine andere Ausgabe dieses Titels beziehen.

Anbieterinformationen

Zur Homepage des Verk�ufers

Unternehmensdaten des Verk�ufers

Edward Bowditch Ltd
Exstowe, Exton, Exeter, EX3 0PP, United Kingdom

Gesch�ftsbedingungen:

Legal entity name: Edward Bowditch Ltd
Legal entity form: Limited company
Business correspondence address: Exstowe, Exton, Exeter, EX3 0PP
Company registration number: 04916632
VAT registration: GB834241546
Authorised representative: Mr. E. Bowditch

Versandinformationen:

Orders usually dispatched within two working days.

Zahlungsarten
akzeptiert von diesem Verk�ufer

Zu Kaufgesuchen hinzuf�gen

Verwandte Artikel zu Integrated Circuit and System Design. Power and Timing...

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 18th International Workshop, Patmos 2008, Lisbon, Portugal, September 10-12, 2008, Proceedings

Svensson, Lars (Editor)/ Monteiro, Jose (Editor)

Neu - Softcover

Unternehmensdaten des Verk�ufers