Druck auf Anfrage Neuware - Printed after ordering - This book is about digital system testing and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms.Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware/software environment facilitates description of complex test programs and test strategies.

Bestandsnummer des Verk�ufers 9781441975478

Verk�ufer kontaktieren

Diesen Artikel melden

Bibliografische Details

Titel: Digital System Test and Testable Design : Using Hdl Models and Architectures
Verlag: Springer Us
Ver�ffentlichungsdatum: 2010
Sprache: Englisch
ISBN-10: 1441975470
ISBN-13: 9781441975478
Bindung: Buch
Zustand: Neu

�ber diesen Titel

Inhaltsangabe

This book is about digital system testing and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms. Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware/software environment facilitates description of complex test programs and test strategies.

�ber die Autorin bzw. den Autor

About the Author Dr. Zainalabedin Navabi is a professor of electrical and computer engineering at Worcester Polytechnic Institute. Dr. Navabi is the author of several textbooks and computer based trainings on VHDL, Verilog and related tools and environments. Dr. Navabi’s involvement with hardware description languages begins in 1976, when he started the development of a register-transfer level simulator for one of the very first HDLs. In 1981 he completed the development of a synthesis tool that generated MOS layout from an RTL description. Since 1981, Dr. Navabi has been involved in the design, definition and implementation of Hardware Description Languages. He has written numerous papers on the application of HDLs in simulation, synthesis and test of digital systems. He started one of the first full HDL courses at Northeastern University in 1990. Since then he has conducted many short courses and tutorials on this subject in the United States and abroad. In addition to being a professor, he is also a consultant to CAE companies. Dr. Navabi received his M.S. and Ph.D. from the University of Arizona in 1978 and 1891, and his B.S. from the University of Texas at Austin in 1975. He is a senior member of IEEE, a member of IEEE Computer Society, member of ASEE, and ACM.

��ber diesen Titel� kann sich auf eine andere Ausgabe dieses Titels beziehen.

Anbieterinformationen

Das Unternehmen AHA-BUCH GmbH: Seit der Gr�ndung von AHA-BUCH im Juli 2005 ist unser Hauptziel, zufriedenen Kunden so schnell und so preisg�nstig wie m�glich ihren B�cherwunsch zu erf�llen. Unsere Firma besch�ftigt 16 Mitarbeiter, die nur ein Ziel kennen: den Kunden und seine W�nsche! Auf �ber 3700 m2 Fl�che haben wir �ber 100.000 B�cher, Modernes Antiquariat und Spiele auf Lager.

Zur Homepage des Verk�ufers

Unternehmensdaten des Verk�ufers

AHA-BUCH GmbH
Garlebsen 48, Einbeck, 37574, Germany

Gesch�ftsbedingungen und Versandinformationen

Verkaufsbedingungen

Allgemeine Gesch�ftsbedingungen und Kundeninformationen / Datenschutzerkl�rung

I. Allgemeine Gesch�ftsbedingungen

� 1 Grundlegende Bestimmungen

(1) Die nachstehenden Gesch�ftsbedingungen gelten f�r alle Vertr�ge, die Sie mit uns als Anbieter (AHA-BUCH GmbH) �ber die Internetplattformen AbeBooks und/oder ZVAB schlie�en. Soweit nicht anders vereinbart, wird der Einbeziehung gegebenenfalls von Ihnen verwendeter eigener Bedingungen widersprochen.

(2) Verbraucher im Sinne der nachstehenden Regelungen...

Mehr Information

Versandbedingungen

Wir liefern Lagerartikel innerhalb von 24 Stunden nach Erhalt der Bestellung aus.
Barsortimentsartikel, die wir �ber Nacht geliefert bekommen, am darauffolgenden Werktag.
Unser Ziel ist es Ihnen die Artikel in der �konomischten und effizientesten Weise zu senden.

Impressum & Info zum Verk�ufer