Large and complicated digital circuits can be incorporated into hardware by using Verilog, a hardware description language (HDL). A designer aspiring to master this versatile language must first become familiar with its constructs, practice their use in real applications, and apply them in combinations in order to be successful. Design Through Verilog HDL affords novices the opportunity to perform all of these tasks, while also offering seasoned professionals a comprehensive resource on this dynamic tool.

Describing a design using Verilog is only half the story: writing test-benches, testing a design for all its desired functions, and how identifying and removing the faults remain significant challenges. Design Through Verilog HDL addresses each of these issues concisely and effectively. The authors discuss constructs through illustrative examples that are tested with popular simulation packages, ensuring the subject matter remains practically relevant.

�ber die Autorin bzw. den Autor

T. R. PADMANABHAN, PhD, is Dean-Engineering, Amrita Institute of Technology, Amrita Vishwa Vidyapeetham, (Amrita University), Ettimadai (PO), Coimbatore, India. He is a Senior Member of IEEE as well as a Fellow of both India’s IE and IETE.

B. BALA TRIPURA SUNDARI is a Senior Lecturer in the ECE Department of the Amrita Institute of Technology. She is a senior faculty member in the microelectronics center at the institute. She is a member of India’s IETE and ISTE.

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