Compilation Techniques for Reconfigurable Architectures

Beschreibung:

An introduction to hardware compilation and reconfigurable computing architectures, this book presents a variety of compiler code transformations and mapping techniques focusing on imperative programming languages. Num Pages: 223 pages, 88 black & white illustrations, biography. BIC Classification: TJF; UYF. Category: (P) Professional & Vocational. Dimension: 234 x 156 x 12. Weight in Grams: 367. . 2010. 1st ed. Softcover of orig. ed. 2009. Paperback. . . . . Books ship from the US and Ireland. Bestandsnummer des Verkäufers V9781441935106

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This book describes a wide range of code transformations and mapping techniques for compiling programs written in high-level programming languages to reconfigurable architectures. While many of these transformations and mapping techniques have been developed in the context of compilation for traditional architectures and high-level synthesis, their application to reconfigurable architectures poses a whole new set of challenges- particularly when targeting fine-grained reconfigurable architectures such as contemporary Field-Programmable Gate-Arrays (FPGAs).

Organized in eight chapters, this book provides a helpful structure for practitioners and graduate students in the area of computer science and electrical and computer engineering to effectively map computations to reconfigurable architectures.

Key Features:

• Introduces the reader to hardware compilation and reconfigurable computing architectures.
• Presents a range of compiler code transformations and mapping techniques focusing on imperative programming languages.
• Allows the reader to bridge the gap between the software compilation and the hardware compilation and synthesis domains.
• Brings a number of compilation techniques together into one structured source, and includes representative examples of their applications.

• Provides a historical perspective on representative compilation research efforts over the last 15 years.