Assertion-Based Design
Foster, Harry D.; Krolnik, Adam C.; Lacey, David
ISBN 10: 1402080271 ISBN 13: 9781402080272
Verlag: Springer-Verlag New York Inc., 2004
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Beschreibung
Beschreibung:
Focuses on how to specify assertions, how to create and adopt a methodology that supports assertion-based design, and what to do with the assertions and methodology. This title offers multiple forms of assertion specifications: Accellera Open Verification Library (OVL), Accellera Property Specification Language (PSL), and Accellera System Verilog. Series: Information Technology: Transmission, Processing and Storage. Num Pages: 390 pages, biography. BIC Classification: UY. Category: (P) Professional & Vocational. Dimension: 241 x 163 x 28. Weight in Grams: 726. . 2004. 2nd ed. 2004. Hardback. . . . . Books ship from the US and Ireland. Bestandsnummer des Verkäufers V9781402080272
Inhaltsangabe:
Chapter 3 Specifying RTL Properties 61 3. 1 Definitions and concepts 62 62 3. 1. 1 Property 3. 1. 2 Events 65 3. 2 Property classification 65 Safety versus liveness 66 3. 2. 1 3. 2. 2 Constraint versus assertion 67 3. 2. 3 Declarative versus procedural 67 3. 3 RTL assertion specification techniques 68 RTL invariant assertions 69 3. 3. 1 3. 3. 2 Declaring properties with PSL 72 RTL cycle related assertions 73 3. 3. 3 3. 3. 4 PSL and default clock declaration 74 3. 3. 5 Specifying sequences 75 3. 3. 6 Specifying eventualities 80 3. 3. 7 PSL built-in functions 82 3. 4Pragma-based assertions 82 3. 5 SystemVerilog assertions 84 3. 5. 1 Immediate assertions 84 3. 5. 2Concurrent assertions 86 3. 5. 3 System functions 95 3. 6 PCI property specification example 96 3. 6. 1 PCI overview 96 3. 7 Summary 102 Chapter 4 PLI-Based Assertions 103 4. 1 Procedural assertions 104 4. 1. 1 A simple PLI assertion 105 4. 1. 2 Assertions within a simulation time slot 108 4. 1. 3 Assertions across simulation time slots 111 4. 1. 4 False firing across multiple time slots 116 4. 2 PLI-based assertion library 118 4. 2. 1 Assert quiescent state 119 4. 3 Summary 123 Chapter 5 Functional Coverage 125 5. 1 Verification approaches 126 5. 2 Understanding coverage 127 5. 2. 1 Controllability versus observability 128 5. 2.
Críticas:
"David Lacey, Harry and Adam are key participants on the Acceller SystemVerilog Standards Group. Their practical verification experience has contributed to the value of the assertion enhancements added to the SystemVerilog standard. These three verification specialists have written a book that will endow the reader with an understanding of the fundamental and important topics needed to comprehend and implement assertion based design. This book is a must for all design and verification engineers."
(Cliff Cummings, Verilog Guru & President, Sunburst Design, Inc.)
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Bibliografische Details
Titel: Assertion-Based Design
Verlag: Springer-Verlag New York Inc.
Erscheinungsdatum: 2004
Einband: Hardcover
Zustand: New
Auflage: 2. Auflage
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Assertion-Based Design (Information Technology: Transmission, Processing & Storage)
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Assertion-Based Design
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Springer US, Springer US Mai 2004, 2004
ISBN 10: 1402080271
ISBN 13: 9781402080272
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Buch. Zustand: Neu. Neuware -Chapter 3 Specifying RTL Properties 61 3. 1 Definitions and concepts 62 62 3. 1. 1 Property 3. 1. 2 Events 65 3. 2 Property classification 65 Safety versus liveness 66 3. 2. 1 3. 2. 2 Constraint versus assertion 67 3. 2. 3 Declarative versus procedural 67 3. 3 RTL assertion specification techniques 68 RTL invariant assertions 69 3. 3. 1 3. 3. 2 Declaring properties with PSL 72 RTL cycle related assertions 73 3. 3. 3 3. 3. 4 PSL and default clock declaration 74 3. 3. 5 Specifying sequences 75 3. 3. 6 Specifying eventualities 80 3. 3. 7 PSL built-in functions 82 3. 4Pragma-based assertions 82 3. 5 SystemVerilog assertions 84 3. 5. 1 Immediate assertions 84 3. 5. 2Concurrent assertions 86 3. 5. 3 System functions 95 3. 6 PCI property specification example 96 3. 6. 1 PCI overview 96 3. 7 Summary 102 Chapter 4 PLI-Based Assertions 103 4. 1 Procedural assertions 104 4. 1. 1 A simple PLI assertion 105 4. 1. 2 Assertions within a simulation time slot 108 4. 1. 3 Assertions across simulation time slots 111 4. 1. 4 False firing across multiple time slots 116 4. 2 PLI-based assertion library 118 4. 2. 1 Assert quiescent state 119 4. 3 Summary 123 Chapter 5 Functional Coverage 125 5. 1 Verification approaches 126 5. 2 Understanding coverage 127 5. 2. 1 Controllability versus observability 128 5. 2.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 420 pp. Englisch. Artikel-Nr. 9781402080272
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Buch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - Chapter 3 Specifying RTL Properties 61 3. 1 Definitions and concepts 62 62 3. 1. 1 Property 3. 1. 2 Events 65 3. 2 Property classification 65 Safety versus liveness 66 3. 2. 1 3. 2. 2 Constraint versus assertion 67 3. 2. 3 Declarative versus procedural 67 3. 3 RTL assertion specification techniques 68 RTL invariant assertions 69 3. 3. 1 3. 3. 2 Declaring properties with PSL 72 RTL cycle related assertions 73 3. 3. 3 3. 3. 4 PSL and default clock declaration 74 3. 3. 5 Specifying sequences 75 3. 3. 6 Specifying eventualities 80 3. 3. 7 PSL built-in functions 82 3. 4Pragma-based assertions 82 3. 5 SystemVerilog assertions 84 3. 5. 1 Immediate assertions 84 3. 5. 2Concurrent assertions 86 3. 5. 3 System functions 95 3. 6 PCI property specification example 96 3. 6. 1 PCI overview 96 3. 7 Summary 102 Chapter 4 PLI-Based Assertions 103 4. 1 Procedural assertions 104 4. 1. 1 A simple PLI assertion 105 4. 1. 2 Assertions within a simulation time slot 108 4. 1. 3 Assertions across simulation time slots 111 4. 1. 4 False firing across multiple time slots 116 4. 2 PLI-based assertion library 118 4. 2. 1 Assert quiescent state 119 4. 3 Summary 123 Chapter 5 Functional Coverage 125 5. 1 Verification approaches 126 5. 2 Understanding coverage 127 5. 2. 1 Controllability versus observability 128 5. 2. Artikel-Nr. 9781402080272
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