Chiplets and Advanced Packaging: Die-to-Die Interconnect, 2.5D and 3D Integration, Hybrid Bonding, and Thermal Design for Multi-Die Systems - Softcover

Inhaltsangabe

Transistor scaling no longer carries a computing system on its own. The gains that matter now come from how dies are partitioned, connected, stacked, powered, and cooled inside one package — and that has turned advanced packaging into a design discipline in its own right. This is the working textbook for that discipline. It opens by deriving the economics that govern every decision — defect density, die cost versus area, composite yield, the assembly-yield penalty, and the point at which splitting a design stops paying — then builds on those numbers through twenty-two rigorously quantitative chapters. You will learn die-to-die links and the UCIe stack through revision 3.0; silicon, organic, and glass-core substrates; embedded bridges and through-silicon vias; copper-to-copper hybrid bonding down to sub-micron pitch; three-dimensional stacking and high-bandwidth memory through HBM4; kilowatt-class power delivery; cooling from interface materials to direct-to-silicon microfluidics; and co-packaged optics.

Unlike reference handbooks, this book teaches. Every chapter carries learning objectives, full derivations with tracked units, worked examples solved with real numbers, and practice problems with complete solutions. More than 150 original figures render every cross-section, scaling law, and tradeoff from first principles. Appendices supply a symbol list, glossary, a standards reference with revision years, materials property tables, and a complete cost-and-yield model. Written for upper-undergraduate and graduate students and for the packaging, integration, and system engineers building multi-die products.

• The economics of disaggregation — yield models, gross-die-per-wafer, known-good-die, and the cost break-even that decides whether to split a chip
• Die-to-die interconnect from first principles (energy per bit, bandwidth density, beachfront) plus UCIe 3.0, Bunch of Wires, and OpenHBI
• The full substrate menu: silicon, organic, and RDL interposers; embedded bridges with TSVs; panel-level and glass-core substrates
• Microbump scaling to its assembly-yield wall, then copper-to-copper hybrid bonding from process integration to sub-micron pitch
• Three-dimensional stacking with active base dies, and high-bandwidth memory through HBM4 with custom base dies
• Power delivery for kilowatt-class packages and thermal design from TIMs to embedded microfluidic cooling
• Co-packaged optics, the multi-die design flow, test and known-good-die, thermomechanical reliability, signal/power integrity, and supply-chain trust

• Teaches instead of cataloging: derivations, worked examples, and fully solved problem sets in every chapter
• Current to the technologies shipping today — UCIe 3.0, HBM4, backside power delivery, hybrid bonding, co-packaged optics
• Quantitative throughout: pitches in micrometers, energy in femtojoules per bit, bandwidth density in GB/s/mm, thermal resistance in K/W
• 150-plus original, self-contained figures — every cross-section and scaling law drawn from the underlying physics
• A complete, reusable cost-and-yield model you can re-run for your own product
• A standards reference with current revision years, so the numbers stay usable

• Upper-undergraduate and graduate students in electrical, computer, and materials engineering
• Packaging, assembly, and heterogeneous-integration engineers moving from monolithic SoCs to multi-die products
• Chip architects and SoC designers now reasoning about partitioning, interposers, and thermal budgets
• Signal/power-integrity, reliability, and test engineers supporting 2.5D and 3D programs
• Instructors building a modern advanced-packaging or heterogeneous-integration course
• Self-learners with a circuits or semiconductor background entering the chiplet field

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