Ultra-Low Energy Domain-Specific Instruction-Set Processors (Embedded Systems) - Softcover

Über die Autorin bzw. den Autor

Anup Kumar Das is an Assistant Professor at Drexel University. He received a Ph.D. in Embedded Systems from National University of Singapore in 2014. Prior to his Ph.D., he was a research engineer for more than 7 years at ST Microelectronics (India and Grenoble) and LSI Corporation (India). Following his Ph.D., he was a post-doctoral fellow at the University of Southampton from 2014 to 2015 and a researcher at IMEC from 2015 to 2017. His research focuses on neuromorphic computing, from algorithm development to architectural exploration.  His other research interests include System-level design techniques for lifetime and energy optimization, Soft-error tolerance of FPGA configuration bitstream, Synchronous data flow graph based task mapping and scheduling, Probabilistic energy and performance optimization of multiprocessor systems, architectural adaptations for lifetime improvement of multiprocessor, and Design-for-testability (DFT) of multi-power domain SoC. AkashKumar is a Professor at TU Dresden.  He received the B.Eng. degree in computer engineering from the National University of Singapore (NUS), Singapore, in 2002, the joint Master of Technological Design degree in embedded systems from NUS and the Eindhoven University of Technology (TUe), Eindhoven, The Netherlands, in 2004, and the joint Ph.D. degree in electrical engineering in the area of embedded systems from TUe and NUS, in 2009. His specialities include multiprocessor architectural design, synchronous dataflow graphs, FPGA tool flows and Xilinx FPGA boards. Bharadwaj Veeravalli, Member, IEEE & IEEE-CS, received his BSc in Physics, from Madurai-Kamaraj University, India in 1987, Master's in Electrical Communication Engineering from Indian Institute of Science, Bangalore, India in 1991 and PhD from Department of Aerospace Engineering, Indian Institute of Science, Bangalore, India in 1994. He received Gold Medals for his Bachelor's Degree overall performance and foran outstanding PhD thesis (Sabitha Chowdhary Gold Medal, IISc, Bangalore India) in the years 1987 and 1994, respectively.. He did his post-doctoral research in the Department of Computer Science, Concordia University, Montreal, Canada, in 1996. He is currently with the Department of Electrical and Computer Engineering, Communications and Information Engineering (CIE) division, at The National University of Singapore, Singapore, as a tenured Associate Professor. His main stream research interests include, Cloud/Grid/Cluster Computing, Scheduling in Parallel and Distributed Systems, Bioinformatics & Computational Biology, and Multimedia Computing. He is one of the earliest researchers in the field of Divisible Load Theory (DLT). He had successfully secured several externally funded projects. He has published over 100 papers in high-quality International Journals and Conferences. He has co-authored three research monographs in the areas of PDS, Distributed Databases (Competitive Algorithms), and Networked Multimedia Systems, in the years 1996, 2003, and 2005, respectively. He had guest edited a special issue on Cluster/Grid Computing for IJCA, USA journal in 2004. He is currently serving the Editorial Board of IEEE Transactions on Computers, IEEE Transactions on SMC-A, Multimedia Tools & Applications (MTAP) and Cluster Computing, as an Associate Editor. He was a Visiting Professor with HUST, Wuhan, China, from June 2007-May 2009. He had served (and serving) as a program committee member and as a Session Chair in several International Conferences. In September 2010, he has been invited to deliver keynote speech in fifth IEEE International Conference on Bio-Inspired Computing: Theory and Applications (BIC-TA) September 2010, held in Changsha, PR China  Francky Catthoor received a Ph.D. in El. Eng. from the K.U.Leuven, Belgium in 1987. Since then, he has headed several research domains in the area of architectural methodologies and system synthesis for embedded multimedia and telecom applications, all with

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Modern consumers carry many electronic devices, like a mobile phone, digital camera, GPS, PDA and an MP3 player. The functionality of each of these devices has gone through an important evolution over recent years, with a steep increase in both the number of features as in the quality of the services that they provide. However, providing the required compute power to support (an uncompromised combination of) all this functionality is highly non-trivial. Designing processors that meet the demanding requirements of future mobile devices requires the optimization of the embedded system in general and of the embedded processors in particular, as they should strike the correct balance between flexibility, energy efficiency and performance. In general, a designer will try to minimize the energy consumption (as far as needed) for a given performance, with a sufficient flexibility. However, achieving this goal is already complex when looking at the processor in isolation, but, in reality, the processor is a single component in a more complex system. In order to design such complex system successfully, critical decisions during the design of each individual component should take into account effect on the other parts, with a clear goal to move to a global Pareto optimum in the complete multi-dimensional exploration space.

In the complex, global design of battery-operated embedded systems, the focus of Ultra-Low Energy Domain-Specific Instruction-Set Processors is on the energy-aware architecture exploration of domain-specific instruction-set processors and the co-optimization of the datapath architecture, foreground memory, and instruction memory organisation with a link to the required mapping techniques or compiler steps at the early stages of the design. By performing an extensive energy breakdown experiment for a complete embedded platform, both energy and performance bottlenecks have been identified, together with the important relations between thedifferent components. Based on this knowledge, architecture extensions are proposed for all the bottlenecks.