This book explores the design and optimization of advanced Surrounding Gate Tunnel Field-Effect Transistors (SGTFETs) for future low-power semiconductor technologies. It presents analytical models and TCAD-based investigations of conventional SGTFETs, Triple Material SGTFETs (TMSGTFETs), and III-V High-k SGTFETs, with emphasis on improving switching performance, reducing leakage, and enhancing energy efficiency. The work integrates evolutionary multiobjective optimization using NSGA-III and machine-learning-assisted Pareto Active Learning to identify optimal trade-offs among delay, dynamic power, on-off current ratio, switching speed, and device variability. By combining device physics, computational intelligence, and optimization techniques, the book offers a scalable framework for the development of high-performance nanoscale transistor architectures suitable for next-generation integrated circuits and emerging nanoelectronic applications.
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Charumathi V is currently working at Thiagarajar College of Engineering (TCE), Madurai, in the field of Electronics and Communication Engineering. She completed her doctoral research at TCE, specializing in advanced Tunnel Field-Effect Transistors (TFETs), TCAD simulation, machine learning, and evolutionary multiobjective optimization.
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PAP. Zustand: New. New Book. Shipped from UK. Established seller since 2000. Artikel-Nr. L2-9786630209815
Anzahl: Mehr als 20 verfügbar