On high-performance embedded computing, we are witnessing the trend to integrate multiple cores in Multi-Processor Systems-on-Chip (MPSoCs). Networks- on-chip (NoCs) have been proposed to be a scalable, predictable and flexible paradigm to design complex NoC-based Many-core MPSoCs. However, since the number of cores increases exponentially, new challenges such as the design of suitable NoCs, and how to exploit parallelism on a chip arise. In this book, we showour EDA tool (xENoC - NoCMaker) that allows design, simulation and fast-prototype of NoC-based systems, as well as the trade-offs on the design of Network Interfaces (NI) to provide interoperability between cores of different protocols (AMBA/OCP-IP) with Quality-of-Service (QoS) support at a reasonable power and area costs. In the second part, the book tries to shed light on system-level software, runtime QoS support and middleware APIs, and a MPI-like parallel programming model (ocMPI), which offers SW programmers a way to express message-passing parallelism on NoC-based MPSoCs. This book should be especially useful for researchers on the field of parallel embedded computing on many- core on-chip systems.
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Mr. Jaume Joven received his M.Sc. (2004) and Ph.D degree (2009) in Computer Science from Universitat Autònoma de Barcelona (UAB). His research interests are focused on HW-SW design of NoC-based MPSoCs, ranging from circuit design up to system-level SW, runtime middleware and parallel programming models. He is currently a postdoc at EPFL.
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Taschenbuch. Zustand: Neu. System-Level Software and Architectural Support for NoC-based MPSoCs | A HW-SW Component View for Many-core Systems | Jaume Joven (u. a.) | Taschenbuch | 228 S. | Englisch | 2011 | LAP LAMBERT Academic Publishing | EAN 9783838334127 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu. Artikel-Nr. 107100904
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