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This volume encompasses the latest, innovative methods of testing three-dimensional integrated circuits, incorporating pre-bond and post-bond tests as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective.
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Krishnendu Chakrabarty is a Professor of Electrical and Computer Engineering at Duke University. He received his PhD from University of Michigan. He is a Fellow of IEEE and a Distinguished Engineer of ACM.
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This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.
Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICs;
Includes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule optimizations;
Encompasses all aspects of test as related to 3D ICs, including pre-bond and post-bond test as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective.
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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
Verlag:
Springer International Publishing, 2016
ISBN 10: 3319345346
ISBN 13: 9783319345345
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Taschenbuch
Anbieter: AHA-BUCH GmbH, Einbeck, Deutschland
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Taschenbuch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable. Artikel-Nr. 9783319345345
Anzahl: 1 verfügbar
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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
ISBN 10: 3319345346
ISBN 13: 9783319345345
Neu
Taschenbuch
Anbieter: buchversandmimpf2000, Emtmannsberg, BAYE, Deutschland
Verkäuferbewertung 5 von 5 Sternen
Taschenbuch. Zustand: Neu. Neuware -This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 264 pp. Englisch. Artikel-Nr. 9783319345345
Anzahl: 2 verfügbar
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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
Anbieter: Revaluation Books, Exeter, Vereinigtes Königreich
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Paperback. Zustand: Brand New. reprint edition. 264 pages. 9.25x6.10x0.62 inches. In Stock. Artikel-Nr. 3319345346
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