Memory Controllers for Real-Time Embedded Systems: Predictable and Composable Real-Time Systems - Softcover

Über die Autorin bzw. den Autor

Sven Goossens received his M.Sc. in Embedded Systems from the Eindhoven University of Technology in 2010. He worked as a researcher in the Electrical Engineering of the same university until 2011, and then started as a Ph.D. student, graduating in 2015. He is currently employed as a Hardware Architect at Intrinsic-ID. His research interests include mixed time-criticality systems, composability and SDRAM controllers.Karthik Chandrasekar earned his M.Sc. degree in Computer Engineering from TU Delft in the Netherlands in November 2009. In October 2014, he received his Ph.D. also from the same university. His research interests include SoC Architectures, DRAM memories & memory controllers, on-chip communication networks and performance & power modeling and analysis. He is currently employed as a Senior Architect at Nvidia. Benny Akesson received his M.Sc. degree at Lund Institute of Technology, Sweden in 2005 and a Ph.D. from Eindhoven University of Technology, the Netherlands in 2010. Since then, he has been employed as a Researcher at Eindhoven University of Technology, Czech Technical University in Prague, and CISTER/INESC TEC Research Unit in Porto. Currently, he is working as a Research Fellow at TNO-ESI. His research interests include memory controller architectures, real-time scheduling, performance modeling, and performance virtualization. He has published more than 50 peer-reviewed conference papers and journal articles, as well as two books about memory controllers for real-time embedded systems. Kees Goossens received his Ph.D. in Computer Science from the University of Edinburgh in 1993. He worked for Philips/NXP Research from 1995 to 2010 on networks-onchips for consumer electronics, where real-time performance, predictability, and costs are major constraints. He was part-time professor at Delft University from 2007 to 2010, and is now full professor at the Eindhoven University of Technology, where his research focuses on composable (virtualized), predictable (real-time), low-power embedded systems, supporting multiple models of computation. He published 4 books, 100+ papers, and 24 patents.

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Verification of real-time requirements in systems-on-chip becomes more complex as more applications are integrated. Predictable and composable systems can manage the increasing complexity using formal verification and simulation. This book explains the concepts of predictability and composability and shows how to apply them to the design and analysis of a memory controller, which is a key component in any real-time system.

This book is generally intended for readers interested in Systems-on-Chips with
real-time applications. It is especially well-suited for readers looking to use SDRAM memories in systems with hard or firm real-time requirements. There is a strong focus on real-time concepts, such as predictability and composability, as well as a brief discussion about memory controller architectures for high-performance computing.

Readers will learn step-by-step how to go from an unpredictable SDRAM memory,
offering highly variable bandwidth and latency, to a predictable and composable
shared memory, providing guaranteed bandwidth and latency to isolated applications.
This journey covers concepts for making memories and arbiters behave in a
predictable and composable manner, as well as architecture descriptions of hardware
blocks that implement the concepts.

• Provides an overview of trends in embedded system design that make design of real-time SoCs difficult, error-prone, and expensive;
• Introduces the concept of predictability, which is required for formal verification of real-time systems;
• Introduces the concept of composability, which is a divide and conquer technique that enables performance verification per application, instead of monolithic verification for all applications together;
• Describes a novel approach to composability, which applies to any predictable shared resource, thus widely extending the scope of composable platforms. This is the first approachthat can efficiently support SDRAM, which is an essential system component;
• Provides an overview of the SDRAM architecture at a level that is relevant for system designers, not memory designers, and explains why SDRAM architectures are difficult to use in real-time systems;
• Describes concepts, architectures, implementation and worst-case performance analysis of predictable SDRAM accesses, as well as predictable and composable memory arbitration, which can be applied to all memory types