Inhaltsangabe
Introduction.- Related Work.- Background.- Architectural Selection using High Level Synthesis.- Statistical Regression Based Power Models.- Coprocessor Design Space Exploration Using High Level Synthesis.- Regression-based Dynamic Power Estimation for FPGAs.- High Level Simulation Directed RTL Power Estimation.- Applying Verification Collaterals for Accurate Power Estimation.- Power Reduction using High-Level Clock-gating.- Model-Checking to exploit Sequential Clock-gating.- System Level Simulation Guided Approach for Clock-gating.- Conclusions.
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