The design process of digital circuits is often carried out in individual steps, like logic synthesis, mapping, and routing. Since originally the complete process was too complex, it has been split up in several - more or less independen- phases. In the last 40 years powerful algorithms have been developed to find optimal solutions for each of these steps. However, the interaction of these different algorithms has not been considered for a long time. This leads to quality loss e. g. in cases where highly optimized netlists fit badly onto the target architecture. Since the resulting circuits are often far from being optimal and insufficient regarding the optimization criteria, like area and delay, several iterations of the complete design process have to be carried out to get high quality results. This is a very time consuming and costly process. For this reason, some years ago the idea of one-pass synthesis came up. There were two main approaches how to guarantee that a design got "first time right" : 1. Combining levels that were split before, e. g. to use layout information already during the logic synthesis phase. 2. Restricting the optimization in one level such that it better fits to the next one. So far, several approaches in these two directions have been presented and new techniques are under development. In this book we describe the new paradigm that is used in one-pass synthesis and present examples for the two techniques above.
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Zustand: Good. Zustand des Schutzumschlags: Good. Kluwer Academic Publishers, 2002. Cover very lightly rubbed, corners very barely rubbed, spine ends lightly rubbed/bumped; binding tight; cover, edges, and interior intact and exceptionally clean. hardcover. Good/Good. Artikel-Nr. 587976
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Zustand: New. Describes the paradigm that is used in one-pass synthesis. This book discusses the theoretical and practical aspects and gives minimization algorithms. Num Pages: 182 pages, biography. BIC Classification: T; UY. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 235 x 155 x 12. Weight in Grams: 1000. . 2002. Hardback. . . . . Books ship from the US and Ireland. Artikel-Nr. V9781402070440
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Buch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - The design process of digital circuits is often carried out in individual steps, like logic synthesis, mapping, and routing. Since originally the complete process was too complex, it has been split up in several - more or less independen- phases. In the last 40 years powerful algorithms have been developed to find optimal solutions for each of these steps. However, the interaction of these different algorithms has not been considered for a long time. This leads to quality loss e. g. in cases where highly optimized netlists fit badly onto the target architecture. Since the resulting circuits are often far from being optimal and insufficient regarding the optimization criteria, like area and delay, several iterations of the complete design process have to be carried out to get high quality results. This is a very time consuming and costly process. For this reason, some years ago the idea of one-pass synthesis came up. There were two main approaches how to guarantee that a design got 'first time right' : 1. Combining levels that were split before, e. g. to use layout information already during the logic synthesis phase. 2. Restricting the optimization in one level such that it better fits to the next one. So far, several approaches in these two directions have been presented and new techniques are under development. In this book we describe the new paradigm that is used in one-pass synthesis and present examples for the two techniques above. Artikel-Nr. 9781402070440
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Zustand: Gut. Zustand: Gut | Sprache: Englisch | Produktart: Bücher | The design process of digital circuits is often carried out in individual steps, like logic synthesis, mapping, and routing. Since originally the complete process was too complex, it has been split up in several - more or less independen- phases. In the last 40 years powerful algorithms have been developed to find optimal solutions for each of these steps. However, the interaction of these different algorithms has not been considered for a long time. This leads to quality loss e. g. in cases where highly optimized netlists fit badly onto the target architecture. Since the resulting circuits are often far from being optimal and insufficient regarding the optimization criteria, like area and delay, several iterations of the complete design process have to be carried out to get high quality results. This is a very time consuming and costly process. For this reason, some years ago the idea of one-pass synthesis came up. There were two main approaches how to guarantee that a design got "first time right" : 1. Combining levels that were split before, e. g. to use layout information already during the logic synthesis phase. 2. Restricting the optimization in one level such that it better fits to the next one. So far, several approaches in these two directions have been presented and new techniques are under development. In this book we describe the new paradigm that is used in one-pass synthesis and present examples for the two techniques above. Artikel-Nr. 1432615/3
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