With this book, you can:
- Start writing synthesizable Verilog models quickly.
- See what constructs are supported for synthesis and how these map to hardware so that you can get the desired logic.
- Learn techniques to help avoid having functional mismatches.
- Immediately start using many of the models for commonly used hardware elements described for your own use or modify these for your own application.
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J. Bhasker is the chair of the IEEE PAR 1364.1 Verilog Synthesis Interoperability Working Group that is working towards standardizing a Verilog subset for RTL synthesis. He is one of the main architects of the Archsyn synthesis system developed at Bell Labs. He has taught Verilog HDL and Verilog HDL synthesis to many AT&T / Lucent designers. He is also the author of the bestselling book "A Verilog HDL Primer"'.Review:
"Bhasker's book reveals a variety of situations where differences between simulation and synthesis semantics are bound to occur. These are carefully covered so that novice and experienced designers become aware of these hard to debug but, very common pitfalls" -- Carlos M. Roman, Bell Labs
"I find the book useful in illustrating examples of how the Verilog language may be used to design real and practical synthesizable models. It's also helpful that it warns the user of possible simulation/ synthesis mismatches. This clarifies the sim/syn issues for beginners." -- Jenjen Tiao, Lucent Technologies
"I've finished reading your book, I have to say I think you did an outstanding job ... I will be very comfortable recommending your book instead ... I really think this is your best book yet, good job!" -- Ken Coffman, VLSI designer
"Provides students and practicing logic designers with immediate access to well organized information about Verilog HDL synthesis. Easy to read and provides a large number of examples of synthesizable Verilog models" -- Vassilios Gerousis, Senior Staff Technologist, Motorola
"The book "A Verilog Synthesis Primer" is an excellent clear and concise guide for designing RTL synthesizable models in Verilog. It is an essential addition to design engineers' technical resourses." -- Douglas J. Smith, author of "HDL Chip Design."
"The example-driven driven approach used in the Verilog HDL Synthesis Primer makes it a valuable book for novice Verilog users." -- Egbert Molenkamp, University of Twente
"This book is ideally organized for teaching Verilog-based synthesis techniques, as it shows the reader not only what hardware results from various Verilog constructs, but how to tailor the Verilog to get the desired hardware. Copious pairings of examples with diagrams make clear the relationships between code and generated gates" -- Jim Vellenga, ViewLogic Systems
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