Reports research promoting a better design approach to testing integrated circuits based on high-level test synthesis, which is able to explore the synthesis freedom provided at a high level to derive an inherently testable architecture at low or even no overhead. Presents several effective schemes for highly testable digital circuits, assuming a non-scan or partial-scan test strategy. These schemes are implemented in the Princeton HI- level Test Synthesis system, which is also presented. Based on a Ph. D. dissertation for Princeton. Double spaced. Annotation c. by Book News, Inc., Portland, Or.
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Dr. Mike Tien-Chien Lee is a software engineer at Avant! Corp. He holds a Ph.D. in electrical engineering from Princeton University. Dr. Lee serves on program committees of IEEE International Test Synthesis Workshop. He received Best Paper Awards at the Asia and South Pacific Design Automation Conference (ASP-DAC) in 1995, and the IEEE/ACM Design Automation Conference (DAC) in 1996.
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