Silicon Wafer Bonding Technology for VLSI and MEMS Applications (Materials, Circuits and Devices) - Hardcover

By bonding a thin wafer of active silicon to a thicker wafer via a layer of insulating oxide to form an SOI structure it is possible to substantially improve the performance and integration of microelectronic circuits produced by very large scale integration (VLSI). For example, the recently announced IBM Power 4 'server-ona- chip' integrates two microprocessors, a high bandwidth system switch, a large memory cache and input/output functions. SOI wafer bonding is also an enabling technology in the rapidly growing field of microelectromechanical systems (MEMS). Engineers who are developing volume production systems employing wafer bonding are in need of guidance from experts in the industry who have been pioneering the field and the book is designed for this purpose. It briefs the process development engineer on the latest emerrging technology, giving the reader the benefit of RandD by companies at the forefront of SOI, and also describes the basic principles. Applications in CMOS, photonics, optoelectronics and MEMS are discussed , there is a glossary of terms used in the field and a table comparing the various bonding methods. Although the main focus is on SOI there is also an appendix which describes a practical silicon-to-silicon bonding process and gives useful information relevant to wafer bonding in general.

Subramanian S. Iyer obtained his B.Tech. in Electrical Engineering at the Indian Institute of Technology, Bombay in 1977, and his M.S. and Ph.D. in Electrical Engineering at the University of California at Los Angeles in 1978 and 1981 respectively. He joined the IBM T.J. Watson Research Center in 1981 and was manager of the Exploratory Structures and Devices Group till 1994, when he founded SiBond L.L.C. to develop and make silicon-on-insulator materials. Since 1997 he has been with the IBM Microelectronics Division, Semiconductor Research and Development Center, where currently he manages the embedded DRAM project. Dr. Iyer has received two outstanding technical achievement awards at IBM for the development of the titanium salicide process and the fabrication of the first SiGe heterojunction bipolar transistor. He has received 15 Invention Achievement Awards and has authored over 150 articles in technical journals and several book chapters. Dr. Iyer is an Adjunct Professor of Electrical Engineering at Columbia University, New York, and a Fellow of the IEEE. Andre J. Auberton-Herve is President Corporate and Chairman of the Board of SOITEC, which is devoted to SOI wafer production. He founded this company with J.M. Lamure in 1992. He holds a Ph.D. in Semiconductor Physics and an M.S. in Materials Science from Ecole Centrale de Lyon. In the 1980s he managed a joint development program between LETI and THOMSON-CSF, the ultimate target of which was the technological transfer from R&D to production of 1.2 m and 0.8 m SOI CMOS for space applications. He was also in charge of several European projects which applied SOI to 3D integration, VLSI and ULSI. In 1999, he received the European SEMI Award in recognition of his work on the Smart Cut (R) technology and his contribution to the semiconductor industry. He is a member of the Electrochemical Society and the IEEE.