Verwandte Artikel zu Formal Semantics for VHDL: 307 (The Springer International...
Formal Semantics for VHDL: 307 (The Springer International Series in Engineering and Computer Science) - Hardcover
Inhaltsangabe
It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verification methods are nowadays supported by several tools, both commercial and academic.
If different tools and users are to generate and read the same language then it is necessary that the same semantics is assigned by them to all constructs and elements of the language. The current IEEE standard VHDL language reference manual (LRM) tries to define VHDL as well as possible in a descriptive way, explaining the semantics in English. But rigor and clarity are very hard to maintain in a semantics defined in this way, and that has already given rise to many misconceptions and contradictory interpretations.
Formal Semantics for VHDL is the first book that puts forward a cohesive set of semantics for the VHDL language. The chapters describe several semantics each based on a different underlying formalism: two of them use Petri nets as target language, and two of them higher order logic. Two use functional concepts, and finally another uses the concept of evolving algebras.
Formal Semantics for VHDL is essential reading for researchers in formal methods and can be used as a text for an advanced course on the subject.
Die Inhaltsangabe kann sich auf eine andere Ausgabe dieses Titels beziehen.
Reseña del editor
It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verification methods are nowadays supported by several tools, both commercial and academic.
If different tools and users are to generate and read the same language then it is necessary that the same semantics is assigned by them to all constructs and elements of the language. The current IEEE standard VHDL language reference manual (LRM) tries to define VHDL as well as possible in a descriptive way, explaining the semantics in English. But rigor and clarity are very hard to maintain in a semantics defined in this way, and that has already given rise to many misconceptions and contradictory interpretations.
Formal Semantics for VHDL is the first book that puts forward a cohesive set of semantics for the VHDL language. The chapters describe several semantics each based on a different underlying formalism: two of them use Petri nets as target language, and two of them higher order logic. Two use functional concepts, and finally another uses the concept of evolving algebras.
Formal Semantics for VHDL is essential reading for researchers in formal methods and can be used as a text for an advanced course on the subject.
„Über diesen Titel“ kann sich auf eine andere Ausgabe dieses Titels beziehen.
Gebraucht kaufen
Zustand: Gut bis sehr gutAncien livre de bibliothèque. Légères...
Diesen Artikel anzeigen
EUR 3,90
EUR 3,99 für den Versand von Frankreich nach Deutschland
Versandziele, Kosten & DauerNeu kaufen
Diesen Artikel anzeigen
EUR 118,64
Gratis für den Versand innerhalb von/der Deutschland
Versandziele, Kosten & Dauer
Suchergebnisse für Formal Semantics for VHDL: 307 (The Springer International...
Beispielbild für diese ISBN
Formal Semantics for Vhdl
Anbieter: Ammareal, Morangis, Frankreich
Verkäuferbewertung 5 von 5 Sternen
Hardcover. Zustand: Bon. Ancien livre de bibliothèque. Légères traces d'usure sur la couverture. Edition 1995. Ammareal reverse jusqu'à 15% du prix net de cet article à des organisations caritatives. ENGLISH DESCRIPTION Book Condition: Used, Good. Former library book. Slight signs of wear on the cover. Edition 1995. Ammareal gives back up to 15% of this item's net price to charity organizations. Artikel-Nr. D-570-521
Anzahl: 1 verfügbar
Foto des Verkäufers
Formal Semantics for VHDL
Anbieter: moluna, Greven, Deutschland
Verkäuferbewertung 5 von 5 Sternen
Gebunden. Zustand: New. It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verifica. Artikel-Nr. 458443725
Anzahl: Mehr als 20 verfügbar
Beispielbild für diese ISBN
Formal Semantics for VHDL (The Springer International Series in Engineering and Computer Science, 307)
Anbieter: Ria Christie Collections, Uxbridge, Vereinigtes Königreich
Verkäuferbewertung 5 von 5 Sternen
Zustand: New. In. Artikel-Nr. ria9780792395522_new
Anzahl: Mehr als 20 verfügbar
Foto des Verkäufers
Formal Semantics for VHDL
Anbieter: AHA-BUCH GmbH, Einbeck, Deutschland
Verkäuferbewertung 5 von 5 Sternen
Buch. Zustand: Neu. Neuware - It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verification methods are nowadays supported by several tools, both commercial and academic. If different tools and users are to generate and read the same language then it is necessary that the same semantics is assigned by them to all constructs and elements of the language. The current IEEE standard VHDL language reference manual (LRM) tries to define VHDL as well as possible in a descriptive way, explaining the semantics in English. But rigor and clarity are very hard to maintain in a semantics defined in this way, and that has already given rise to many misconceptions and contradictory interpretations. Formal Semantics for VHDL is the first book that puts forward a cohesive set of semantics for the VHDL language. The chapters describe several semantics each based on a different underlying formalism: two of them use Petri nets as target language, and two of them higher order logic. Two use functional concepts, and finally another uses the concept of evolving algebras. Formal Semantics for VHDL is essential reading for researchers in formal methods and can be used as a text for an advanced course on the subject. Artikel-Nr. 9780792395522
Anzahl: 2 verfügbar