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Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.
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Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.
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Formal Semantics and Proof Techniques for Optimizing VHDL Models
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Hardcover. Zustand: Très bon. Ancien livre de bibliothèque avec équipements. Edition 1999. Ammareal reverse jusqu'à 15% du prix net de cet article à des organisations caritatives. ENGLISH DESCRIPTION Book Condition: Used, Very good. Former library book. Edition 1999. Ammareal gives back up to 15% of this item's net price to charity organizations. Artikel-Nr. G-454-703
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Formal Semantics and Proof Techniques for Optimizing VHDL Models
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Zustand: New. pp. 184 52:B&W 6.14 x 9.21in or 234 x 156mm (Royal 8vo) Case Laminate on White w/Gloss Lam. Artikel-Nr. 7547249
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Formal Semantics And Proof Techniques For Optimizing Vhdl Models (Hb)
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Zustand: New. This is a Brand-new US Edition. This Item may be shipped from US or any other country as we have multiple locations worldwide. Artikel-Nr. ABNR-77944
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Formal Semantics and Proof Techniques for Optimizing VHDL Models
Anbieter: Anybook.com, Lincoln, Vereinigtes Königreich
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Zustand: Good. This is an ex-library book and may have the usual library/used-book markings inside.This book has hardback covers. In good all round condition. No dust jacket. Please note the Image in this listing is a stock photo and may not match the covers of the actual item,550grams, ISBN:9780792383758. Artikel-Nr. 4137484
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Formal Semantics and Proof Techniques for Optimizing VHDL Models
Verlag:
Springer US, Springer New York Nov 1998, 1998
ISBN 10: 0792383753
ISBN 13: 9780792383758
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Anbieter: buchversandmimpf2000, Emtmannsberg, BAYE, Deutschland
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Buch. Zustand: Neu. Neuware -Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions.Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 184 pp. Englisch. Artikel-Nr. 9780792383758
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Formal Semantics and Proof Techniques for Optimizing VHDL Models
Verlag:
Springer US, Springer New York, 1998
ISBN 10: 0792383753
ISBN 13: 9780792383758
Neu
Hardcover
Anbieter: AHA-BUCH GmbH, Einbeck, Deutschland
Verkäuferbewertung 5 von 5 Sternen
Buch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions. Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL. Artikel-Nr. 9780792383758
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Formal Semantics and Proof Techniques for Optimizing VHDL Models
Anbieter: Ria Christie Collections, Uxbridge, Vereinigtes Königreich
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Zustand: New. In. Artikel-Nr. ria9780792383758_new
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