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Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints.
Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.
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Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints.
Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.
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Logic Synthesis for Low Power VLSI Designs
Verlag:
Kluwer Academic Publishers, Boston, 1998
ISBN 10: 0792380762
ISBN 13: 9780792380764
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hardcover. Zustand: Very Good. Zustand des Schutzumschlags: No Dust Jacket. Name from previous owner on FEP. No dust jacket. Binding is very well preserved, pages clean and and crisp, and printing is tight, clean and bright throughout. Not noticeably different from like new. MB. Used. Artikel-Nr. 248540
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Logic Synthesis for Low Power VLSI Designs
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Logic Synthesis for Low Power VLSI Designs
Verlag:
Springer US, Springer New York Nov 1997, 1997
ISBN 10: 0792380762
ISBN 13: 9780792380764
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Hardcover
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Buch. Zustand: Neu. Neuware -Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints.Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 256 pp. Englisch. Artikel-Nr. 9780792380764
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Logic Synthesis for Low Power VLSI Designs
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Buch. Zustand: Neu. Druck auf Anfrage Neuware - Printed after ordering - Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints. Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis. Artikel-Nr. 9780792380764
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Logic Synthesis for Low Power VLSI Designs
Anbieter: Kennys Bookstore, Olney, MD, USA
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Zustand: New. Provides detailed presentations of methodologies, algorithms and CAD tools for power modelling, estimation and analysis, synthesis and optimization at the logic level. It is designed for engineers, CAD professionals, and students with a basic knowledge of CMOS digital design and logic synthesis. Num Pages: 236 pages, biography. BIC Classification: TJF; UK. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 15. Weight in Grams: 1190. . 1997. Hardback. . . . . Books ship from the US and Ireland. Artikel-Nr. V9780792380764
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