VHDL Design Representation and Synthesis: 2nd Edition (Prentice Hall Modern Semiconductor Design Series'sub Series: Ph Signal Integrity Library) - Softcover

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DR. JAMES R. ARMSTRONG and DR. F. GAIL GRAY are Professors of Electrical and Computer Engineering at Virginia Tech. Dr. Armstrong teaches graduate and undergraduate courses in computer architecture, HDLs, and logic design. He was a member of the original IEEE standardization committee; authored Chip Level Modeling With VHDL, and co-authored Structured Logic Design With VHDL, both from Prentice Hall. Dr. Gray teaches graduate and undergraduate courses in computer engineering, logic design, hardware description languages, coding theory, fault tolerant computing, testing, and microprocessor system design. His work has been published by IEEE Transactions on Computers; Journal of VLSI Signal Processing for Signal, Image, and Video Technology; Design Automation Conference; the VHDL International Users Forum; and many other leading journals and conferences.

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VHDL Design Representation and Synthesis, Second Edition is an exceptionally clear, thorough, and up-to-date introduction to today's leading approach to hardware design: synthesis using a hardware description language and today's leading synthesis tools. Armstrong and Gray begin with an introduction to structured design, and a unified explanation of the VHDL language and its key constructs. Next, they introduce the modeling process step by step, using many examples at varying levels of abstraction, and demonstrate techniques designed to maximize both simulation efficiency and compatibility with synthesis tools.

• Design tools: editors, simulators, checkers, analyzers, optimizers, and synthesizers

• VHDL: major constructs, lexical description, source files, data types, data objects, statements, and advanced features

• Fundamental VHDL modeling techniques: propagation and time delay, concurrency, scheduling, combinational logic, sequential logic, and primitives

• Integrating VHDL into the design flow, from executable specifications at the algorithmic level through implementations at the gate or cell level

• Modling PLDs, gate arrays, FPGAs (using Xilinx tools) and standard cells (using Synopsys tools)

This edition contains extensive new coverage of multilevel modeling, design with standard parts and ASICs data and control unit design, modeling for synthesis, and more. Review problems are included in each chapter, and over 300 references are provided. If you intend to design with VHDL, this is the book to start with.