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Inhaltsangabe
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today s digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.
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By Richard Munden
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Today it is still very difficult to verify board or larger system designs through simulation or any other technique. This important book addresses the largest ingredient needed to make simulation possiblethe availability of integrated circuit component models. Addressed inside is how to use VITAL extensions and other conventions with VHDL to develop interoperable, reusable models. Only by adopting the standards and practices described in this book can the industry benefit and make system simulation feasible.
Randy Harr, Sevni Technology
This book provides not only an excellent reference for those who write component models for board level verification, but also a much needed introduction to SDF and VITAL for timing simulation.
Hardy Pottinger, University of Missouri-Rolla
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs.
ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.
Features
*Provides numerous models and a clearly defined methodology for performing board-level simulation.
*Covers the details of modeling for verification of both logic and timing.
*First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.|Today it is still very difficult to verify board or larger system designs through simulation or any other technique. This important book addresses the largest ingredient needed to make simulation possiblethe availability of integrated circuit component models. Addressed inside is how to use VITAL extensions and other conventions with VHDL to develop interoperable, reusable models. Only by adopting the standards and practices described in this book can the industry benefit and make system simulation feasible.
Randy Harr, Sevni Technology
This book provides not only an excellent reference for those who write component models for board level verification, but also a much needed introduction to SDF and VITAL for timing simulation.
Hardy Pottinger, University of Missouri-Rolla
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs.
ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.
Features
*Provides numerous models and a clearly defined methodology for performing board-level simulation.
*Covers the details of modeling for verification of both logic and timing.
*First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.
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- VerlagMorgan Kaufmann
- Erscheinungsdatum2004
- ISBN 10 0125105819
- ISBN 13 9780125105811
- EinbandTapa dura
- SpracheEnglisch
- Anzahl der Seiten340
- Kontakt zum HerstellerNicht verfügbar
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ASIC and FPGA Verification: A Guide to Component Modeling (Systems on Silicon)
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ASIC & FPGA VERIFICATION
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Elsevier LTD, Oxford, 2004
ISBN 10: 0125105819
ISBN 13: 9780125105811
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Kartoniert / Broschiert
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Kartoniert / Broschiert. Zustand: New. Demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. This book illustrates how ASICs and FPGAs can be verified in the larger context of a board or a syste. Artikel-Nr. 594359561
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ASIC and FPGA Verification : A Guide to Component Modeling
Verlag:
Elsevier Science & Technology Okt 2004, 2004
ISBN 10: 0125105819
ISBN 13: 9780125105811
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Taschenbuch. Zustand: Neu. Neuware - Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today s digital designs.ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.\*Provides numerous models and a clearly defined methodology for performing board-level simulation.\*Covers the details of modeling for verification of both logic and timing.\*First book to collect and teach techniques for using VHDL to model 'off-the-shelf' or 'IP' digital components for use in FPGA and board-level design verification. Artikel-Nr. 9780125105811
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ASIC and FPGA Verification: A Guide To Component Modeling
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Hardcover. Zustand: Brand New. 316 pages. 9.25x7.50x1.00 inches. In Stock. Artikel-Nr. x-0125105819
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